Cypress launches PSoC 3 and PSoC 5 architectures, revolutionizes embedded design!

SAN JOSE, USA: Cypress Semiconductor Corp. today announced two new architectures in its PSoC programmable system-on-chip platform that dramatically increase performance and extend the world’s only programmable analog and digital embedded design platform delivering unmatched time-to-market, integration, and flexibility across 8-, 16-, and 32-bit applications.Source: Cypress

This new programmable analog and digital embedded design platform is powered by the revolutionary PSoC Creator Integrated Development Environment, which introduces a unique schematic-based design capture along with fully tested, pre-packaged analog and digital peripherals easily customizable through user-intuitive wizards and APIs to meet specific design requirements.

The PSoC Creator enables engineers to design the way they think and dramatically shorten time-to-market.

More information, including data sheets, application notes, online training, development kits, free PSoC Creator downloads and device samples, is available at www.cypress.com/go/psoc.

The unique programmable analog and digital peripherals in PSoC 3 and PSoC 5, along with new high performance 8-bit and 32-bit MCU sub-systems, enable new capabilities such as motor control, intelligent power supply and battery management, human interfaces such as CapSense touch sensing, LCD segment display, graphics control, as well as audio/voice processing, communication protocols, and much more.

These new capabilities dramatically expand the markets that PSoC can address, including industrial, medical, automotive, communications and consumer equipment. The total available market for PSoC products is now expanded to over fifteen billion dollars, spanning across 8-, 16- and 32-bit applications, as well as precision analog markets.

The new PSoC 3 and PSoC 5 architectures include high-precision, programmable analog resources that can be configured as ADCs, DACs, TIAs, Mixers, PGAs, OpAmps, and more.

They include enhanced programmable-logic based digital resources that can be configured as 8-, 16-, 24- and 32-bit timers, counters, and PWMs, as well as more advanced digital peripherals such as Cyclic Redundancy Check (CRC), Pseudo Random Sequence (PRS) generators, and quadrature decoders.

Designers have a unique ability to customize this digital system through full featured general purpose PLD-based logic available in PSoC 3 and PSoC 5. The new architectures also support a wide range of communications interfaces, including Full-Speed USB, I2C, SPI, UART, CAN, LIN, and I2S.

The new PSoC 3 and PSoC 5 architectures are powered by high performance, industry-standard processors. The PSoC 3 architecture is based on a new, high-performance 8-bit 8051 processor with up to 33 MIPS, while the PSoC 5 architecture includes a powerful 32-bit ARM Cortex-M3 processor with up to 100 DMIPS.

Both architectures meet the demands of extremely low power applications by delivering the industry’s widest voltage range from 5.5V down to 0.5V along with low 200nA hibernate current. They provide a seamless, programmable design platform from 8- to 32-bit architectures with pin and API compatibility between PSoC 3 and PSoC 5, along with programmable routing, allowing any signal, whether analog or digital, to be routed to any general-purpose I/O to ease circuit board layout. This capability includes the ability to route LCD Segment Display and CapSense signals to any GPIO pin.

“These new families, along with the revolutionary PSoC Creator Software, will change the way embedded designers solve problems,” said T.J. Rodgers, Cypress’s President and CEO. “The PSoC 3 and PSoC 5 architectures deliver a scalable platform with the computing power of high-performance MCUs, the precision of stand-alone analog devices and the flexibility of PLDs, all with a powerful, easy-to-use design environment. This combination gives designers of 8-, 16- and 32-bit applications the flexibility and integration of true ‘system-level’ programmability for the first time.”

“The PSoC is the only architecture that extends the concept of programmability beyond instructions for the processor to configuring peripherals and customization of digital functions,” said Tom Starnes, principal analyst at Objective Analysis in Austin, Texas. “Coupled with analog precision on-chip beyond that found in any other MCU, these highly-integrated PSoCs are more highly-programmable than any other chip. The addition of precision analog and the ARM Cortex processor to the family should bring the performance needed for any modern application.”

Features of PSoC 3 and PSoC 5 architectures

Programmable Precision Analog Sub-system
* Up to 20-bit resolution for Delta-Sigma ADC.
* Sample rates up to 1 MSPS in 12-bit SAR ADC.
* Reference voltage accurate to +/- 0.1% over industrial temperature and voltage range.
* Up to four 8-bit resolution, 8 Msps DACs; 1x to 50x PGA; general purpose Op-amps with 25mA drive capability; up to four comparators with 30 ns response time.
* DSP-like digital filter implementation for instrumentation and medical signal processing.
* Large library of pre-characterized analog peripherals in PSoC Creator Software
CapSense functionality on all devices.

Programmable High-Performance Digital Sub-system
* Array of “Universal Digital Blocks” (UDBs) each consisting of a combination of uncommitted logic (PLD), structured logic (datapath), and flexible routing to other UDBs, I/O or peripherals.
* Large library of pre-characterized digital peripherals in PSoC Creator Software such as 8-, 16-, 24- and 32-bit Timers, Counters, PWMs.
* Ability to customize digital system through full featured general purpose PLD-based logic.
* High-Speed Connectivity: Full Speed USB, I2C, SPI, UART, CAN, LIN, I2S.

High-Performance CPU Sub-systems
* 8-bit 8051 core with 33 MIPS performance (PSoC 3).
* 32-bit ARM Cortex-M3 core with 100 MIPS performance (PSoC 5).
* 24-Channel multilayer Direct Memory Access (DMA) with simultaneous access to SRAM and CPU.
* On-chip debug and trace functionality with JTAG and Serial Wire Debug (SWD).
* Complete Ecosystem of industry-standard compilers and real time operating systems.

Industry Leading Low Power
* Industry’s widest operating range of 0.5V to 5.5V with no degradation in analog performance.
* Active power consumption: 1.2mA at 6 MHz (PSoC 3) and 2mA at 6 MHz (PSoC 5).
* Sleep-mode power consumption: 1µA (PSoC 3) and 2µA (PSoC 5).
* Hibernate-mode power consumption: 200nA (PSoC 3) and 300nA (PSoC 5).

Programmable, Feature-Rich I/O and Clocking
* The ultimate flexibility with any pin to any analog or digital peripheral
LCD Segment Display on any pin with up to 16-commons/736 segments.
* CapSense on any pin for replacing mechanical buttons and sliders.
* 1.2V to 5.5V I/O interface voltages, up to 4 domains for easy interface with systems running at different voltage domains.
* 1 to 66 MHz internal +/-1% oscillator with PLL over full temperature and voltage range.

Sample and kit availability
Samples of the PSoC 3 devices are available today, with full production expected in the first quarter of 2010. The architecture includes three families with varying amounts of memory, digital and analog performance.

Package options include 100-pin TQFPs, 48- and 68-pin QFNs, and 48-pin SSOPs. PSoC 5 samples will be available in the first quarter of 2010 with full production in the second half of the year. The PSoC 5 architecture includes four different families.