SAN JOSE, USA: Cadence Design Systems Inc. has teamed with the Semiconductor Technology Academic Research Center (STARC), a Japanese design consortium, and created an innovative new Cadence-based 32/28-nanometer design-for-manufacturing (DFM) flow.
Using the award-winning Encounter Digital Implementation (EDI) System as the end-to-end implementation vehicle, the in-design DFM flow built into STARC’s STARCAD-CEL methodology enabled chip DFM signoff up to 100 times faster than traditional industry DFM methods.
The productivity gains STARC enjoyed were the result of moving the DFM steps into the implementation stage of chip development and deploying new pattern-matching technology rather than the traditional model-based approach. The new flow extends Cadence’s longtime collaboration with STARC into the 32/28-nanometer arena and further expands its Silicon Realization offerings.
The in-design flow for implementation is focused on maintaining designers’ intent and leveraging accurate abstraction of manufacturing models and rules to deliver blazing fast silicon convergence for DFM variability hotspots. The flow encompasses all elements for hotspot prevention, optimization, and silicon-accurate fixing. The flow makes use of ground-breaking, extremely accurate abstraction technology from core Cadence Silicon Realization tools—including NanoRoute’s litho prevention, Litho Physical Analyzer, CMP Predictor and Layout-Dependent-Effect Electrical Analyzer.
The DFM offering tightly integrates and concurrently optimizes in conjunction with other in-design signoff capabilities already inside EDI System, such as extraction, timing, signal integrity, and power analysis. These capabilities provide the ultimate in risk reduction for yield-limiting DFM hotspots while considering the bigger context of overall systematic and random physical and electrical variability.
“To cope with the complexity of designing at 32/28 nanometers, we had to set aggressive performance and quality targets for accelerating the convergence of DFM issues to address both physical and electrical variability,” said Nobuyuki Nishiguchi, vice president and general manager of development at STARC.
“With the new in-design DFM flow, the targets were surpassed with dramatic time savings, and at no cost to quality. The ability to accurately model and optimize for DFM during design enabled us to do intelligent, preventative work during digital implementation, thereby avoiding time-consuming iterations at signoff. STARC's hierarchical design approach and pattern matching performed world-class litho analysis and resulted in 100 times faster than a full simulation-based litho analysis. STARC believes that this flow is the most practical methodology for 32/28 nanometers and below.”
As an example, with STARC now fully deploying the Cadence Silicon Realization technology, design teams can leverage Encounter DFM’s advanced analysis capability in which abstracts silicon failures or variability hotspots into patterns while maintaining the original design intent.
This accurate abstraction helped STARC reduce the DFM analysis turnaround time during digital implementation with EDI System by 100 times compared to traditional standalone signoff methods. In addition, STARC achieved 100 percent DFM hotspot silicon convergence given the accuracy of the in-design DFM technology, saving several days of DFM error iteration cycle time.
Aligned with the EDA360 vision, the flow supports the Cadence goal of delivering a complete end-to-end Silicon Realization product line that offers unified intent, abstraction and convergence.
“This latest collaboration with STARC has produced a flow that meets stringent accuracy requirements and can save design teams valuable cycle time and risk as they prepare to hand their design over for manufacturing,” said David Desharnais, group director of product management at Cadence. “Our multiple, successful collaborations with STARC around Cadence Silicon Realization have resulted in advanced flows and methodologies that enable technology companies to tighten the profitability gap as well as the productivity gap.”