GSI Technology intros revolutionary next generation SRAM architecture

SANTA CLARA, USA: GSI Technology announced the availability of SigmaQuad-IIIe and SigmaDDR-IIIe, two new SRAM products whose revolutionary architecture provides the ultimate in system performance, reliability, and flexibility for applications that require a high random address rate.

They are specifically designed to meet the growing memory requirements of networking systems -— the backbone of the Internet.

"To most of the world, 'fast memory' means high bandwidth data, while in SRAM circles it has typically meant low latency," said David Chapman, Vice President of Marketing and Applications Engineering for GSI. "But today, networking system designers need something more. The IIIe family delivers more, including the first memory product ever that can sustain continuous fully random read and write transactions every single nanosecond.

"This sort of capability is terribly important to those wishing to measurably enhance the performance of networking systems," noted Chapman.

"And because these parts allow designers to solve problems directly rather than through increasing architectural complexity, these SRAMs help cut development costs and improve our customer’s time-to-market. Although improvement in random address rate — the measure of how often a new fully random access can be executed in a memory device — is sure to be seen as the biggest contribution of this product family, the series also includes the highest bandwidth SRAMs available on the open market and the most complete set of signal integrity improvement tools SRAM users have ever had."

At 625 MHz, the new 72Mbit Type–IIIe products feature the market’s fastest available Burst of 4 operation, which is 14 percent faster than the nearest competitor, and the market's fastest Burst of 2 operation, which is 50 percent faster than the nearest competitor.

Packaged in a 260 BGA with checkerboard power and ground pin out, these devices deliver both high transaction rate operations and very high data bandwidth with dramatically improved signal integrity to control system noise. Additionally, new features have been added to ease host memory controller design and reduce Soft Error Rate (SER).

GSI’s SigmaQuad/SigmaDDR-IIIe devices offer both obvious and subtle improvements over previous generations of Quad and DDR SRAM products. An improved input clocking scheme provides the ability to optimize input setup and hold times in a variety of board layout schemes and an improved output clocking scheme provides a more consistent and therefore a wider data output valid window.

In addition, user-configurable output echo clocks can be centered or edge-aligned. There is also a selectable read pipeline length to maximize input clock frequency. Another feature is highly robust input termination available on all synchronous inputs to minimize signal reflections.

GSI Technology's 72Mbit SigmaQuad/SigmaDDR-IIIe products are sampling now.