HENDERSON, USA: Aldec Corp., a leader in RTL Simulation and EDA, has announced its latest Design Rule Checking application, ALINT 2009.10.
The product includes “best-practice” design rules for fast design closure of safety critical DO-254/ED-80 Avionics designs. ALINT 2009.10 offers a set of VHDL or Verilog design rules optimized to detect HDL code, design and verification issues including: design recoding practices, design reviews and safe synthesis guidelines. The new DO-254 design rule plug-in provides guidance to help achieve DO-254/ED-80 compliance for FPGA designs that reside within a system.
ALINT 2009.10 with VHDL or Verilog DO-254 design rule plug-in is available today and is sold directly from Aldec and its authorized worldwide distributors. Download a free 10-day evaluation copy at: http://www.aldec.com/Downloads/default.aspx.
ALINT is design rule checking software for fast design closure. ALINT analyzes and detects issues early in the design and verification cycle, and checks HDL source code of complex ASIC, FPGA and SoC designs.
It detects such problems as poor coding styles, improper clock and reset management, simulation and synthesis problems, poor testability and source code issues throughout the design flow.