WILSONVILLE, USA: Mentor Graphics Corp. announced that Taiwan Semiconductor Manufacturing Co. (TSMC) selected the Calibre physical verification platform for its Integrated Sign-Off (ISO) Flow, which integrates tools, setup files, and flow management utilities to provide mutual customers with an automated design solution for implementing their chips in TSMC technologies.
The new flow is now available for 65nm designs with planned extensions into other process technology nodes.
According to ST Juang, senior director of Design Infrastructure Marketing at TSMC, "Integrated Sign-Off Flow leverages our close partnership with eco-system partners to provide customers with a proven path to targeted TSMC silicon process. We include key physical verification tools from the Calibre platform in the flow, which we use ourselves for advanced designs and are now making available for our customers."
Design companies face the critical challenge of allocating scarce internal resources to validate libraries, EDA tools and design flows for each specific process node, resulting in potential delays in getting designs released to production.
Recognizing the importance and need for production-quality design flows, TSMC and Mentor are addressing this issue by providing design flows that seamlessly integrate Mentor’s Calibre nmDRC and Calibre nmLVS products for design rule and layout vs. schematic checking. The Calibre platform provides high performance and scalability to reduce turnaround time for the most advanced SoC designs at 65nm and beyond.
"As a close partner with TSMC, we see substantial benefits for our mutual customers by providing a complete design flow, which includes Mentor’s sign-off technologies to help achieve faster turnaround, lower overall design cost, and improved manufacturability," said Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics.
Friday, October 23, 2009
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