MOS-AK/GSA modeling working group holds workshop in San Francisco

SAN JOSE, USA: The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, held its annual winter workshop on December 8, 2010 in San Francisco, California.

More than 50 international academic researchers and modeling engineers attended 11 technical compact modeling presentations. The workshop was co-sponsored by Accelicon Technologies and Cascade Microtech, with technical sponsorship provided by the IEEE Electron Devices Society (EDS), COMON and the Global Semiconductor Alliance (GSA).

Tim K. Smith, CEO of Accelicon Technologies, said: “The highly respected MOS-AK/GSA modeling workshop provides a common forum where experts in the field convene. Device modeling experts from the industry, universities and electronic design automation solution providers share practical best practices, theoretical advances and design automation topics. The knowledge sharing, technical feedback and professional networking from this workshop propagates understanding of transistor behavior and development of advanced modeling and simulation techniques.”

Modeling experts Ian Getreu of IG Associates and Larry Nagel of Omega Enterprises Consulting chaired the workshop’s morning and afternoon sessions, respectively.

David E. Root of Agilent Technologies presented “Time and Frequency Domain Transistor Modeling Based on Nonlinear Vector Network Analyzer Data,” outlining three new radio frequency (RF) nonlinear transistor modeling flows based on large-signal data available from modern nonlinear vector network analyzer (NVNA) instruments.

Speaker Marek Mierzwinski of Tiburon Design Automation discussed RF model development with Verilog‐A standardization in a presentation titled “Developing Verilog‐A Models for RF Simulation.”

Speaking about today’s advancements in modeling, Gennady Gildenblat from Arizona State University (ASU) presented “Compact Model of Independent Gate Asymmetric DGFET,” and Darsen Lu representing the University of California (UC) Berkeley presented “A Multi-Gate CMOS Compact Model – BSIMMG.”

The event featured additional technical presentations covering compact model development, implementation, deployment and standardization. These contributions were made by leading academic and industrial experts, including Michael O. Peralta, Medtronic; individuals from the Ngspice Development Team, Sapienza-Universita di Roma and Simon Fraser University; Brian Chen, Accelicon Technologies; ToeNaing Swe, Cascade Microtech; individuals from the Federal University of Santa Catarina Brazil; Yuri Mahotin, M+Technologies; and Saravana Maruthamuthu, Infineon Technologies, India.

The MOS-AK/GSA Modeling Working Group has various deliverables and initiatives planned for 2011 including a book entitled "Open Source/GNU Computer-aided Design (CAD) for Compact Modeling" and a Verilog-A directory with models and supporting CAD software.