USA: ELECTRONICS.CA PUBLICATIONS, the electronics industry market research and knowledge network, recently announced the availability of a new report entitled "Electronic Chemicals and Materials: The Global Market".
Electronic chemicals and materials are solid, liquid, and gaseous substances used in the fabrication of semiconductors and printed circuit boards (PCBs). Global demand for electronic chemicals and materials, particularly in developed countries, is projected to increase at a CAGR of 12.6 percent through 2015.
The increase in demand for electronic chemicals and materials is related to overall growth in the production of electronic devices, as well as technological innovation that will create opportunities for new materials. New materials such as Low-k dielectrics and advanced photoresists will see growth rates well above average, and opportunities will also emerge in existing technologies as chemical compositions are improved to attain better compatibility and lower costs.
The report addresses the global market for electronic chemicals and materials during the period from 2009 through 2015. It covers the entire range of chemicals and materials that are used in the fabrication of ICs and PCBs.
Highlights of the report:
• The global electronic chemicals and materials market was estimated at $24.6 billion in 2009 and $28.5 billion in 2010. This market is expected to reach $51.6 billion in 2015, a CAGR of 12.6 percent over the 2010-2015 forecast period.
• Wafer demand is projected to increase more than 20 percent in 2010 to approximately $14.7 billion, after declining by nearly 40 percent to $12.2 billion in 2009. It is expected that the market will reach $26.7 billion by 2015, a CAGR of 12.7 percent between 2010 and 2015.
• Demand for polymers and conductive polymers in the electronics industry will grow at a projected CAGR of 26 percent, from an estimated $1.9 billion in 2010 to about $5.9 billion in 2015. Most of the projected growth is attributable to conductive polymers.
Monday, January 31, 2011
Analog Devices’ SPICE simulation tool upgrade allows engineers to design larger, complex circuits and import models
NORWOOD, USA: Analog Devices Inc. (ADI) and National Instruments (NI) collaborated on a new release of NI’s Multisim component evaluation tool with added features and functionality to provide engineers with an easy-to-use environment for the simulation of linear circuits using ADI components.
The free component evaluation tool is available on ADI’s website. Download a copy of the Multisim SPICE Simulation Program at http://www.analog.com/multisim.
Two important feature enhancements available in this edition of the component evaluation tool allow engineers to design larger, more complex circuits and easily import their own models into the tool. By matching more than 1,000 of ADI’s amplifiers, switches and voltage references to over 550 of NI’s simulation models, designers have free access to the industry’s premier simulation environment allowing them to easily experiment with circuit designs and reduce system development time and cost.
SPICE simulation and component evaluation made easy
“With this custom version of the NI Multisim simulation environment, engineers can take a graphical approach to evaluating many of ADI’s industry-leading linear analog components. The result is the flexibility and creative freedom to quickly improve design decisions,” said Bhavesh Mistry, general manager, National Instruments Electronics Workbench Group.
“Engineers working to tight schedules and budgets can avoid costly and time-consuming re-design work due to component choice by enhancing productivity with this SPICE simulator.”
The free component evaluation tool is available on ADI’s website. Download a copy of the Multisim SPICE Simulation Program at http://www.analog.com/multisim.
Two important feature enhancements available in this edition of the component evaluation tool allow engineers to design larger, more complex circuits and easily import their own models into the tool. By matching more than 1,000 of ADI’s amplifiers, switches and voltage references to over 550 of NI’s simulation models, designers have free access to the industry’s premier simulation environment allowing them to easily experiment with circuit designs and reduce system development time and cost.
SPICE simulation and component evaluation made easy
“With this custom version of the NI Multisim simulation environment, engineers can take a graphical approach to evaluating many of ADI’s industry-leading linear analog components. The result is the flexibility and creative freedom to quickly improve design decisions,” said Bhavesh Mistry, general manager, National Instruments Electronics Workbench Group.
“Engineers working to tight schedules and budgets can avoid costly and time-consuming re-design work due to component choice by enhancing productivity with this SPICE simulator.”
High-speed 8-bit A/D converters deliver best-in-class power and noise performance
NORWOOD, USA: Analog Devices Inc. (ADI), a global leader in high-performance signal processing and the data converter market share leader, has released two 8-bit, high-speed, low-power, low-noise A/D converters (analog-to-digital converters) designed for instrumentation and communications applications.
Both 8-bit high-speed A/D converters use a pipeline architecture and consume an industry-best 310 mW of power.
The AD9284 is the industry’s first dual, 8-bit, 250-MSPS A/D converter while the AD9286 8-bit 500-MSPS A/D converter delivers 8-bit resolution at 40 percent less power than competitive components. The converters feature high SNR (signal-to-noise ratio) of 49.3 dBFS and allow for a wide dynamic signal range with SFDR (spurious-free dynamic range) performance of 65 dBc. Applications for these components include battery-powered instruments, handheld scope meters and digital oscilloscopes.
The AD9286 and AD9284 can be used with ADI’s ADA4960 low-distortion, ultra-high-speed differential A/D converter driver and the AD9516 clock generator to provide a data conversion signal chain solution.
Both 8-bit high-speed A/D converters use a pipeline architecture and consume an industry-best 310 mW of power.
The AD9284 is the industry’s first dual, 8-bit, 250-MSPS A/D converter while the AD9286 8-bit 500-MSPS A/D converter delivers 8-bit resolution at 40 percent less power than competitive components. The converters feature high SNR (signal-to-noise ratio) of 49.3 dBFS and allow for a wide dynamic signal range with SFDR (spurious-free dynamic range) performance of 65 dBc. Applications for these components include battery-powered instruments, handheld scope meters and digital oscilloscopes.
The AD9286 and AD9284 can be used with ADI’s ADA4960 low-distortion, ultra-high-speed differential A/D converter driver and the AD9516 clock generator to provide a data conversion signal chain solution.
Apache Design Solutions releases next gen chip power model for broader range of apps
SAN JOSE, USA: Apache Design Solutions, providing the industry’s leading power and noise solutions for Chip-Package-System (CPS) convergence from RTL to sign-off, announced the release of CPM v2.0, its next generation Chip Power Model (CPM) intended for true co-analysis/co-optimization of the chip, package, and system.
Ideal for wireless and automotive markets, including 3D IC and SiP designs, the release of CPM v2.0 expands the range of coverage to include system resonance awareness, the power transition impact on a global power delivery network (PDN), thermal co-analysis, and EMI and EMC validation. It also delivers user configurable models for an effective CPS flow.
“Apache pioneered the market with its first delivery of CPM, and as adoption and application of the model continues to grow, our close partnership with customers has driven us to provide more advanced features to meet their needs,” said Andrew Yang, CEO of Apache Design Solutions.
“Our franchise in the IC power domain and the market leadership of RedHawk has provided Apache with the unique position to deliver the most comprehensive, accurate, and usable die model for chip-package-system convergence.”
Broader range of applications
Apache’s resonance-aware CPM v2.0 model considers the LC resonance frequency of the system and automatically generates an on-die switching scenario operating at or near the system resonance.
This unique capability enables system designers to access a CPM representing the worst case switching scenario that can be used for stress testing the CPS design. By using resonance-aware models, designers can determine the optimal placement and configuration of the package and PCB decoupling capacitance to help manage power and noise.
CPM v2.0 models on-die power transient waveform over a long duration to capture the envelope modulating the high frequency switching. This represents middle to low frequency components on the chips which impacts the global PDN and needs to be handled by package and PCB power supply system. The power transition model allows system designers to simulate load step conditions to identify and debug weaknesses in their package and system designs.
In 3D-IC and SiP designs, thermal integrity becomes a major challenge for chip-package-system co-design. The power mapping in CPM v2.0 enables package designers to accurately predict the thermal distribution and hot spots of multiple die in a stacked die packaging.
In automotive and wireless markets, using on-chip LDO voltage regulators is increasing, but a key design concern is EMI and EMC. The expanded capability of CPM v2.0 delivers a power model that contains the LDO circuitry that is critical to system-level EMI and EMC validation.
Enhanced usability
Apache’s CPM v2.0 offers enhanced usability with user configurable models for system-level ‘what-if’ analysis of various IC switching scenarios. Chip designers can create multiple current profiles for various blocks within the design, enabling system designers to simulate power switching scenarios and exhaustively verify their system.
In addition, CPM v2.0 adds probing of internal nodes for interactive dynamic power analysis. This provides system designers with access to the critical areas of chip for enhanced debugging and optimization.
Ideal for wireless and automotive markets, including 3D IC and SiP designs, the release of CPM v2.0 expands the range of coverage to include system resonance awareness, the power transition impact on a global power delivery network (PDN), thermal co-analysis, and EMI and EMC validation. It also delivers user configurable models for an effective CPS flow.
“Apache pioneered the market with its first delivery of CPM, and as adoption and application of the model continues to grow, our close partnership with customers has driven us to provide more advanced features to meet their needs,” said Andrew Yang, CEO of Apache Design Solutions.
“Our franchise in the IC power domain and the market leadership of RedHawk has provided Apache with the unique position to deliver the most comprehensive, accurate, and usable die model for chip-package-system convergence.”
Broader range of applications
Apache’s resonance-aware CPM v2.0 model considers the LC resonance frequency of the system and automatically generates an on-die switching scenario operating at or near the system resonance.
This unique capability enables system designers to access a CPM representing the worst case switching scenario that can be used for stress testing the CPS design. By using resonance-aware models, designers can determine the optimal placement and configuration of the package and PCB decoupling capacitance to help manage power and noise.
CPM v2.0 models on-die power transient waveform over a long duration to capture the envelope modulating the high frequency switching. This represents middle to low frequency components on the chips which impacts the global PDN and needs to be handled by package and PCB power supply system. The power transition model allows system designers to simulate load step conditions to identify and debug weaknesses in their package and system designs.
In 3D-IC and SiP designs, thermal integrity becomes a major challenge for chip-package-system co-design. The power mapping in CPM v2.0 enables package designers to accurately predict the thermal distribution and hot spots of multiple die in a stacked die packaging.
In automotive and wireless markets, using on-chip LDO voltage regulators is increasing, but a key design concern is EMI and EMC. The expanded capability of CPM v2.0 delivers a power model that contains the LDO circuitry that is critical to system-level EMI and EMC validation.
Enhanced usability
Apache’s CPM v2.0 offers enhanced usability with user configurable models for system-level ‘what-if’ analysis of various IC switching scenarios. Chip designers can create multiple current profiles for various blocks within the design, enabling system designers to simulate power switching scenarios and exhaustively verify their system.
In addition, CPM v2.0 adds probing of internal nodes for interactive dynamic power analysis. This provides system designers with access to the critical areas of chip for enhanced debugging and optimization.
SandForce Trusted program accelerates time-to-market for SandForce Driven SSD manufacturers and system OEMs
MILPITAS, USA: SandForce Inc., the pioneer of SSD (Solid State Drive) Processors that enable standard NAND flash deployment in enterprise, client, and industrial computing applications, has launched the SandForce Trusted program.
The new program highlights companies that provide equipment, tools, and services compatible with SandForce SSD Processors, and enables SSD manufacturers and system OEMs to receive first class service and support when developing SandForce-based solutions, further accelerating overall SSD market adoption.
“We know that time-to-market is critical in the fast-moving computing world, especially in the quickly expanding SSD market. That is why we created this highly organized ‘Approved Vendor List’ to enable our customers to get the highest level of support during their product design and production phases,” said Kent Smith, senior director of Product Marketing for SandForce.
“Building on the overwhelming success of the SandForce Driven program that easily identifies SandForce-based solutions to end users, this new program identifies companies that are dedicated to supporting the successful and rapid proliferation of SandForce products and technology market-wide.”
Seven prominent SandForce Trusted charter members include companies that provide premier products and services in their respective fields of expertise. The companies initially participating are: Calypso Systems, Granite River Labs, LeCroy, OakGate Technology, Serial Cables, SerialTek and ULINK Technology.
Each member ensures that their products and/or services fully support SandForce SSD Processors and provides response to SandForce customer inquiries within 24 hours while committing to high-priority support for fastest problem resolution. A new SandForce Trusted logo easily identifies program members in their advertising and promotional materials.
The new program highlights companies that provide equipment, tools, and services compatible with SandForce SSD Processors, and enables SSD manufacturers and system OEMs to receive first class service and support when developing SandForce-based solutions, further accelerating overall SSD market adoption.
“We know that time-to-market is critical in the fast-moving computing world, especially in the quickly expanding SSD market. That is why we created this highly organized ‘Approved Vendor List’ to enable our customers to get the highest level of support during their product design and production phases,” said Kent Smith, senior director of Product Marketing for SandForce.
“Building on the overwhelming success of the SandForce Driven program that easily identifies SandForce-based solutions to end users, this new program identifies companies that are dedicated to supporting the successful and rapid proliferation of SandForce products and technology market-wide.”
Seven prominent SandForce Trusted charter members include companies that provide premier products and services in their respective fields of expertise. The companies initially participating are: Calypso Systems, Granite River Labs, LeCroy, OakGate Technology, Serial Cables, SerialTek and ULINK Technology.
Each member ensures that their products and/or services fully support SandForce SSD Processors and provides response to SandForce customer inquiries within 24 hours while committing to high-priority support for fastest problem resolution. A new SandForce Trusted logo easily identifies program members in their advertising and promotional materials.
Avago debuts 28-nm ASIC embedded SerDes with industry-leading 30-Gbps performance
DesignCon 2011, SAN JOSE, USA. & SINGAPORE: Avago Technologies, a leading supplier of analog interface components for communications, industrial and consumer applications, announced that it has demonstrated 30-Gbps performance with its new Serializer/Deserializer (SerDes) core in 28-nm process technology.
The company also announced it has shipped over 150 million embedded SerDes channels integrated in Application-Specific Integrated Circuits (ASICs) used for data communication in networking, computing and storage applications. The milestones reflect the growing demand for increased bandwidth for servers, routers and other data center equipment.
Avago will demonstrate 30-Gbps speeds with its 28-nm SerDes in the LeCroy booth (#307) at the DesignCon 2011 exhibition in the Santa Clara Convention Center in Santa Clara, California from February 1-2.
“Cloud computing, virtualization and the proliferation of large video files have data center equipment manufacturers keenly focused on expanding bandwidth,” said Sergis Mushell, principal research analyst at Gartner. “For semiconductor companies, integration and manufacturing prowess are keys to keeping pace with data rate requirements in this space.”
“Avago customers have been well pleased by our ability to deliver first-time-right ASIC silicon, which played a big part in surpassing 150 million SerDes cores shipped,” said Frank Ostojic, VP and GM of the ASIC Products Division at Avago. “We have repeatedly set new industry standards for performance benchmarks with our SerDes cores to help data center equipment OEMs keep up with bandwidth demands.”
In November 2010, Avago announced it was first to demonstrate 28-Gbps SerDes performance in 40-nm Complementary Metal–Oxide–Semiconductor (CMOS) process technology. Avago will also exhibit its 40-nm SerDes in the Tyco Electronics booth (#515) and the Amphenol booth (#101) at DesignCon 2011.
Avago Intellectual Property (IP) SerDes cores can be easily integrated due to their modular, multirate architecture. Avago is able to integrate up to 400 SerDes channels or over 190 million gates on a single ASIC, with transistor counts in excess of 4 billion. The Avago SerDes cores feature a unique decision feedback equalization (DFE) architecture, resulting in a number of key performance differentiators such as low overall power, best-in-class data latency, and best-in-class jitter and crosstalk tolerance.
The company also announced it has shipped over 150 million embedded SerDes channels integrated in Application-Specific Integrated Circuits (ASICs) used for data communication in networking, computing and storage applications. The milestones reflect the growing demand for increased bandwidth for servers, routers and other data center equipment.
Avago will demonstrate 30-Gbps speeds with its 28-nm SerDes in the LeCroy booth (#307) at the DesignCon 2011 exhibition in the Santa Clara Convention Center in Santa Clara, California from February 1-2.
“Cloud computing, virtualization and the proliferation of large video files have data center equipment manufacturers keenly focused on expanding bandwidth,” said Sergis Mushell, principal research analyst at Gartner. “For semiconductor companies, integration and manufacturing prowess are keys to keeping pace with data rate requirements in this space.”
“Avago customers have been well pleased by our ability to deliver first-time-right ASIC silicon, which played a big part in surpassing 150 million SerDes cores shipped,” said Frank Ostojic, VP and GM of the ASIC Products Division at Avago. “We have repeatedly set new industry standards for performance benchmarks with our SerDes cores to help data center equipment OEMs keep up with bandwidth demands.”
In November 2010, Avago announced it was first to demonstrate 28-Gbps SerDes performance in 40-nm Complementary Metal–Oxide–Semiconductor (CMOS) process technology. Avago will also exhibit its 40-nm SerDes in the Tyco Electronics booth (#515) and the Amphenol booth (#101) at DesignCon 2011.
Avago Intellectual Property (IP) SerDes cores can be easily integrated due to their modular, multirate architecture. Avago is able to integrate up to 400 SerDes channels or over 190 million gates on a single ASIC, with transistor counts in excess of 4 billion. The Avago SerDes cores feature a unique decision feedback equalization (DFE) architecture, resulting in a number of key performance differentiators such as low overall power, best-in-class data latency, and best-in-class jitter and crosstalk tolerance.
Latest release of Synopsys IC compiler delivers faster design closure
MOUNTAIN VIEW, USA: Synopsys Inc. has announced the availability of the latest release of IC Compiler, a key component of the Galaxy Implementation Platform.
This development caps a year of leading innovations in physical design productivity. For two years in a row, IC Compiler has won an EDN Innovation Award. In 2010 it won for In-Design Physical Verification. The IC Compiler 2010.12 release advances this capability, making automatic DRC repair up to 7X faster.
This latest release also delivers new performance improvements for multicorner/multimode (MCMM) designs bringing the total for the year to a nearly 4X speed-up. Additionally, IC Compiler 2010.12 introduces technology specifically targeted for final top-level design closure, helping accelerate turnaround-time by 2X to 3X. Finally, IC Compiler 2010.12 delivers quality-of-results (QoR) improvements, focusing on power reduction.
"With our 28 nanometer Stratix V FPGAs, we have pushed the boundaries of performance, density and integration," said Brad Howe, VP of IC engineering at Altera. "IC Compiler's key technologies such as concurrent multicorner/multimode (MCMM) optimization and In-Design automatic DRC repair were a strong enabler for us to achieve our performance and area targets, allowing us to meet our tight design schedule."
Power-sensitive designers have access to a powerful leakage optimization engine integrated in IC Compiler. Recommended for final-stage leakage recovery on a close-to-tapeout design, this engine is architected to deal with a multitude of cell variants to deliver optimal leakage reduction while preserving timing.
This release also delivers up to 10 percent lower out-of-the-box clock tree power and a 10 percent reduction in total buffer count for reduced dynamic power consumption. Additional QoR improvements include advances in clock feasibility, signal integrity and electro-migration closure.
The IC Compiler 2010.12 release continues to improve runtime performance, delivering an additional 1.5X speed-up along with a 20 percent reduction in memory. On-Demand Loading technology (ODL), first introduced to significantly reduce time-to-floorplan creation, has been extended to top-level closure to accelerate turnaround-time by 2X to 3X.
Using ODL, concurrent optimization of top and block interfaces enables blocks to be adjusted transparently, reducing the need for costly feedback loops between top-level and block-level implementation. IC Compiler In-Design physical verification technology dramatically reduces design iterations by enabling signoff-accurate DRC analysis and repair during design. In this release, incremental revalidation of repair regions and improved fix rates result in up to 7X faster automatic DRC repair times.
"The latest IC Compiler release demonstrates our strong focus on technology innovation that delivers compelling customer value," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "In the high-end FPGA market where time to market is a key differentiator, IC Compiler In-Design technology has successfully addressed one of Altera's key design productivity concerns."
This development caps a year of leading innovations in physical design productivity. For two years in a row, IC Compiler has won an EDN Innovation Award. In 2010 it won for In-Design Physical Verification. The IC Compiler 2010.12 release advances this capability, making automatic DRC repair up to 7X faster.
This latest release also delivers new performance improvements for multicorner/multimode (MCMM) designs bringing the total for the year to a nearly 4X speed-up. Additionally, IC Compiler 2010.12 introduces technology specifically targeted for final top-level design closure, helping accelerate turnaround-time by 2X to 3X. Finally, IC Compiler 2010.12 delivers quality-of-results (QoR) improvements, focusing on power reduction.
"With our 28 nanometer Stratix V FPGAs, we have pushed the boundaries of performance, density and integration," said Brad Howe, VP of IC engineering at Altera. "IC Compiler's key technologies such as concurrent multicorner/multimode (MCMM) optimization and In-Design automatic DRC repair were a strong enabler for us to achieve our performance and area targets, allowing us to meet our tight design schedule."
Power-sensitive designers have access to a powerful leakage optimization engine integrated in IC Compiler. Recommended for final-stage leakage recovery on a close-to-tapeout design, this engine is architected to deal with a multitude of cell variants to deliver optimal leakage reduction while preserving timing.
This release also delivers up to 10 percent lower out-of-the-box clock tree power and a 10 percent reduction in total buffer count for reduced dynamic power consumption. Additional QoR improvements include advances in clock feasibility, signal integrity and electro-migration closure.
The IC Compiler 2010.12 release continues to improve runtime performance, delivering an additional 1.5X speed-up along with a 20 percent reduction in memory. On-Demand Loading technology (ODL), first introduced to significantly reduce time-to-floorplan creation, has been extended to top-level closure to accelerate turnaround-time by 2X to 3X.
Using ODL, concurrent optimization of top and block interfaces enables blocks to be adjusted transparently, reducing the need for costly feedback loops between top-level and block-level implementation. IC Compiler In-Design physical verification technology dramatically reduces design iterations by enabling signoff-accurate DRC analysis and repair during design. In this release, incremental revalidation of repair regions and improved fix rates result in up to 7X faster automatic DRC repair times.
"The latest IC Compiler release demonstrates our strong focus on technology innovation that delivers compelling customer value," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "In the high-end FPGA market where time to market is a key differentiator, IC Compiler In-Design technology has successfully addressed one of Altera's key design productivity concerns."
TriQuint unveils latest broadband WCDMA solution for ST-Ericsson platforms
Mobile World Congress 2011, HILLSBORO, USA & BARCELONA, SPAIN: TriQuint Semiconductor Inc., a leading RF front-end product manufacturer and foundry services provider, has introduced a new member to its TRIUMF Module family, the TQM7M9070.
Its advanced integration technology offers 3G designers building global smartphones and other mobile devices a streamlined RF footprint, through support for multiple modulations and multiple bands in one module. This broadband power amplifier module aligns with ST-Ericsson’s MM5730 and U5500 platforms.
In addition to reducing the component count, the featured power amplifier provides WCDMA/HSUPA modulation over multiple bands by enabling outstanding Power Added Efficiency (PAE) without requiring a DC to DC converter. Power amplifier PAE is a critical contributor to longer battery life and greatly enhances the user experience of mobile devices.
In close collaboration with ST-Ericsson, all system-critical parameters will be verified as a platform reference design. “Customers can be assured the solution has been tested and works together to deliver a new level of power added efficiency,” said Tim Dunn, VP and GM of Mobile Devices at TriQuint. “Given the real estate limitations in today’s devices, our new broadband power amplifier module offers a competitive advantage to our customers since it reduces the transmit area by more than 20 percent, and optimizes the electrical RF performance for each unique device.”
TriQuint’s broadband power amplifier supports WCDMA high bands 1, 2 & 4, and WCDMA low bands 5, 6 & 8. Its scalability from dual-band to penta-band applications addresses the demand for mid to high-end feature and smartphones. Enabled by TriQuint’s CuFlip technology, the broadband PAM inherently manages heat in a remarkably small form factor, 5x4x1mm3.
Complementary to TQM7M9070, TriQuint offers a highly-efficient quad-band power amplifier module, the TQM7M5022R, for GSM/EDGE to support a complete amplification solution for any cellular multimode/multiband application.
Its advanced integration technology offers 3G designers building global smartphones and other mobile devices a streamlined RF footprint, through support for multiple modulations and multiple bands in one module. This broadband power amplifier module aligns with ST-Ericsson’s MM5730 and U5500 platforms.
In addition to reducing the component count, the featured power amplifier provides WCDMA/HSUPA modulation over multiple bands by enabling outstanding Power Added Efficiency (PAE) without requiring a DC to DC converter. Power amplifier PAE is a critical contributor to longer battery life and greatly enhances the user experience of mobile devices.
In close collaboration with ST-Ericsson, all system-critical parameters will be verified as a platform reference design. “Customers can be assured the solution has been tested and works together to deliver a new level of power added efficiency,” said Tim Dunn, VP and GM of Mobile Devices at TriQuint. “Given the real estate limitations in today’s devices, our new broadband power amplifier module offers a competitive advantage to our customers since it reduces the transmit area by more than 20 percent, and optimizes the electrical RF performance for each unique device.”
TriQuint’s broadband power amplifier supports WCDMA high bands 1, 2 & 4, and WCDMA low bands 5, 6 & 8. Its scalability from dual-band to penta-band applications addresses the demand for mid to high-end feature and smartphones. Enabled by TriQuint’s CuFlip technology, the broadband PAM inherently manages heat in a remarkably small form factor, 5x4x1mm3.
Complementary to TQM7M9070, TriQuint offers a highly-efficient quad-band power amplifier module, the TQM7M5022R, for GSM/EDGE to support a complete amplification solution for any cellular multimode/multiband application.
Synopsys Galaxy Implementation platform addresses gigascale design
MOUNTAIN VIEW, USA: Synopsys Inc. has announced the 2010.12 release of its Galaxy Implementation Platform, delivering new technologies to address the scalability, convergence and throughput needs of "Gigascale" design.
Faster runtime performance with multicore processing and innovations to increase design capacity throughout the Galaxy Platform enable engineering teams to gain productivity benefits for large-scale, complex integrated circuit (IC) design. Additionally, the Galaxy Platform includes comprehensive foundry-validated 28-nanometer (nm) silicon process node support for all routing and design rule checking (DRC) rules, extraction and lithography requirements.
The Galaxy 2010.12 release is available now.
Increasing demand for consumer electronics, like smartphones, media tablets and Internet-connected HDTVs, is driving semiconductor companies to rapidly implement massively integrated, multimillion-instance Gigascale IC designs. Thanks to the convergence of logic synthesis, physical implementation and signoff into an integrated platform, Synopsys' Galaxy Platform delivers the scalability and throughput that are essential to implement the largest ICs, designed for the most advanced process technologies.
Key components of the Galaxy Platform include:
Design Compiler Graphical with IC Compiler: Provides faster RTL-to-physical convergence from initial design exploration through concurrent multi-corner/multi-mode (MCMM) optimization, and closure for timing, power, testability and area;
IC Compiler's Zroute technology: Offers concurrent design for manufacturability (DFM) routing for advanced process technologies. Coupled with In-Design physical verification via IC Validator enables the fastest multicore, lithography-aware routing and delivers full compliance with complex DRC rules required for advanced silicon nodes; and
PrimeTime HyperScale technology: Speeds block-level timing closure in the context of the top-level design, dramatically accelerating signoff of complex, hierarchical designs.
Among core technology enhancements, the Galaxy 2010.12 release delivers significant runtime and capacity improvements, including:
RTL Synthesis: Reduction of total negative timing slack in DC Ultra averaging 25 percent, resulting in increased design closure predictability.
Physical Implementation: Extended on-demand loading (ODL) technology in IC Compiler for two to three times (2-3X) faster top-level physical design closure.
Seven times (7X) faster In-Design automatic DRC repair
Signoff: Twenty percent runtime and memory improvements in PrimeTime.
New capabilities in PrimeTime to support SPICE-accurate clock mesh analysis, an essential technology required for designs with embedded processor cores.
Enhancements to PrimeTime HyperScale technology delivering runtime efficiencies for designs with multiply-instantiated blocks.
One-and-a-half times (1.5X) faster parasitic extraction with StarRC.
RTL-to-GDSII: New buffer tree creation and aggressive area recovery techniques result in an average 10 percent reduction in buffer and inverter cells, providing power, routability and area improvements.
"The next generation of Gigascale SoC devices requires a high throughput implementation solution with multimillion-instance capacity and rapid convergence for design closure," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "The 2010.12 release of our Galaxy Platform provides designers with a comprehensive solution to address their advanced needs, including support for the most advanced 28-nanometer process technologies."
The Galaxy Implementation Platform 2010.12 is available immediately. Synopsys' Lynx Design System, the most comprehensive and automated environment for implementing chips, includes a production-proven RTL-to-GDSII design flow that now fully supports the 2010.12 release of Galaxy tools as well as pre-validated foundry-ready system technology plug-ins for popular process technologies.
Faster runtime performance with multicore processing and innovations to increase design capacity throughout the Galaxy Platform enable engineering teams to gain productivity benefits for large-scale, complex integrated circuit (IC) design. Additionally, the Galaxy Platform includes comprehensive foundry-validated 28-nanometer (nm) silicon process node support for all routing and design rule checking (DRC) rules, extraction and lithography requirements.
The Galaxy 2010.12 release is available now.
Increasing demand for consumer electronics, like smartphones, media tablets and Internet-connected HDTVs, is driving semiconductor companies to rapidly implement massively integrated, multimillion-instance Gigascale IC designs. Thanks to the convergence of logic synthesis, physical implementation and signoff into an integrated platform, Synopsys' Galaxy Platform delivers the scalability and throughput that are essential to implement the largest ICs, designed for the most advanced process technologies.
Key components of the Galaxy Platform include:
Design Compiler Graphical with IC Compiler: Provides faster RTL-to-physical convergence from initial design exploration through concurrent multi-corner/multi-mode (MCMM) optimization, and closure for timing, power, testability and area;
IC Compiler's Zroute technology: Offers concurrent design for manufacturability (DFM) routing for advanced process technologies. Coupled with In-Design physical verification via IC Validator enables the fastest multicore, lithography-aware routing and delivers full compliance with complex DRC rules required for advanced silicon nodes; and
PrimeTime HyperScale technology: Speeds block-level timing closure in the context of the top-level design, dramatically accelerating signoff of complex, hierarchical designs.
Among core technology enhancements, the Galaxy 2010.12 release delivers significant runtime and capacity improvements, including:
RTL Synthesis: Reduction of total negative timing slack in DC Ultra averaging 25 percent, resulting in increased design closure predictability.
Physical Implementation: Extended on-demand loading (ODL) technology in IC Compiler for two to three times (2-3X) faster top-level physical design closure.
Seven times (7X) faster In-Design automatic DRC repair
Signoff: Twenty percent runtime and memory improvements in PrimeTime.
New capabilities in PrimeTime to support SPICE-accurate clock mesh analysis, an essential technology required for designs with embedded processor cores.
Enhancements to PrimeTime HyperScale technology delivering runtime efficiencies for designs with multiply-instantiated blocks.
One-and-a-half times (1.5X) faster parasitic extraction with StarRC.
RTL-to-GDSII: New buffer tree creation and aggressive area recovery techniques result in an average 10 percent reduction in buffer and inverter cells, providing power, routability and area improvements.
"The next generation of Gigascale SoC devices requires a high throughput implementation solution with multimillion-instance capacity and rapid convergence for design closure," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "The 2010.12 release of our Galaxy Platform provides designers with a comprehensive solution to address their advanced needs, including support for the most advanced 28-nanometer process technologies."
The Galaxy Implementation Platform 2010.12 is available immediately. Synopsys' Lynx Design System, the most comprehensive and automated environment for implementing chips, includes a production-proven RTL-to-GDSII design flow that now fully supports the 2010.12 release of Galaxy tools as well as pre-validated foundry-ready system technology plug-ins for popular process technologies.
AWR releases AWR connected for ODB++ and extends reach of PCB design
DesignCon 2011, EL SEGUNDO, USA: AWR Corp., the innovation leader in high-frequency EDA software, has released a new product within its AWR Connected portfolio, specifically an ODB++ PCB layout verification design flow for connecting popular third-party PCB tools with its Microwave Office (MWO) and AXIEM software solutions.
The ODB++ PCB flow specifically moves layout data from a customer’s PCB vendor tool into a relevant and independent file format ready for use and import into AWR software, extending its compatibility to popular firms such as Altium, Intercept and Zuken.
This new ODB++ compatibility solution not only transfers important intelligence from the PCB layout/database into Microwave Office, but it also gives the user the ability to selectively import either by net or by region. This selective filtering allows the engineer to focus on the design’s most critical aspects, and by reducing the amount of unnecessary data passed to the simulator, this importer also reduces set up and simulation time.
Highlights include:
* Import layout from PCB tools for EM analysis; full PCB, arbitrary section, and/or select traces with proximity;
* Schematic automatically created from component information (i.e. models supplied by designer);
* Apply EM ports and wire automatically into schematic; and
* Complements existing AWR Connected bidirectional flow with Mentor Graphics that support full co-design at all stages.
The ODB++ PCB flow specifically moves layout data from a customer’s PCB vendor tool into a relevant and independent file format ready for use and import into AWR software, extending its compatibility to popular firms such as Altium, Intercept and Zuken.
This new ODB++ compatibility solution not only transfers important intelligence from the PCB layout/database into Microwave Office, but it also gives the user the ability to selectively import either by net or by region. This selective filtering allows the engineer to focus on the design’s most critical aspects, and by reducing the amount of unnecessary data passed to the simulator, this importer also reduces set up and simulation time.
Highlights include:
* Import layout from PCB tools for EM analysis; full PCB, arbitrary section, and/or select traces with proximity;
* Schematic automatically created from component information (i.e. models supplied by designer);
* Apply EM ports and wire automatically into schematic; and
* Complements existing AWR Connected bidirectional flow with Mentor Graphics that support full co-design at all stages.
Microchip’s Bluetooth kit provides easy and cost-effective method for evaluating and adding Bluetooth connectivity to embedded designs
CHANDLER, USA: Microchip Technology Inc., a leading provider of microcontroller, analog and Flash-IP solutions, announced the Microchip Bluetooth Evaluation Kit, which includes CandleDragon Inc.’s dotstack demonstration Bluetooth Stack.
The kit provides an easy, cost-effective and flexible add-on for embedded evaluation and development using many 16/32-bit PIC microcontrollers or dsPIC digital signal controllers (DSCs). To speed development and further reduce costs, the Microchip Bluetooth Kit works with the company’s existing tools.
While Bluetooth wireless technology is a common short-range protocol for PCs and consumer electronics, it is rapidly gaining popularity among a broader set of embedded applications. However, the current Bluetooth wireless technology modules are costly and inflexible because they force developers to use their predetermined baseband radio and microcontroller.
Microchip and CandleDragon’s Bluetooth solution enables designers to pair a wide range of radio ICs for Bluetooth connectivity with many of Microchip’s 16/32-bit PIC microcontrollers or dsPIC DSCs. Additionally, CandleDragon’s dotstack Bluetooth stack is Bluetooth SIG compliant and supports multiple profiles in a single microcontroller—including SPP, HFP and HID—with more profiles planned for Microchip’s MCUs in the near future.
“Microchip makes it easy for our customers to cost-effectively evaluate and add Bluetooth wireless technology to their designs, with minimal development time and low risk,” said Mitch Obolsky, vice president of Microchip’s Advanced Microcontroller Architecture Division. “Our new Microchip Bluetooth Evaluation Kit, combined with CandleDragon’s Bluetooth Stack, goes one step further in enabling embedded Bluetooth connectivity.”
The kit provides an easy, cost-effective and flexible add-on for embedded evaluation and development using many 16/32-bit PIC microcontrollers or dsPIC digital signal controllers (DSCs). To speed development and further reduce costs, the Microchip Bluetooth Kit works with the company’s existing tools.
While Bluetooth wireless technology is a common short-range protocol for PCs and consumer electronics, it is rapidly gaining popularity among a broader set of embedded applications. However, the current Bluetooth wireless technology modules are costly and inflexible because they force developers to use their predetermined baseband radio and microcontroller.
Microchip and CandleDragon’s Bluetooth solution enables designers to pair a wide range of radio ICs for Bluetooth connectivity with many of Microchip’s 16/32-bit PIC microcontrollers or dsPIC DSCs. Additionally, CandleDragon’s dotstack Bluetooth stack is Bluetooth SIG compliant and supports multiple profiles in a single microcontroller—including SPP, HFP and HID—with more profiles planned for Microchip’s MCUs in the near future.
“Microchip makes it easy for our customers to cost-effectively evaluate and add Bluetooth wireless technology to their designs, with minimal development time and low risk,” said Mitch Obolsky, vice president of Microchip’s Advanced Microcontroller Architecture Division. “Our new Microchip Bluetooth Evaluation Kit, combined with CandleDragon’s Bluetooth Stack, goes one step further in enabling embedded Bluetooth connectivity.”
NetLogic doubles IPv6 processing capabilities in 40nm
SANTA CLARA, USA: NetLogic Microsystems Inc. has announced the expansion of its IPv6 knowledge-based processor portfolio with the introduction of its NL82048 processor which doubles the IPv6 processing capabilities for next-generation switches and routers.
The exponential growth in the number of connected mobile devices, services and applications for next-generation LTE deployments are driving the global migration from IPv4 to IPv6 network architectures.
In order to support this migration to IPv6, as well as the continued increases in complexity and higher throughputs of network traffic, next-generation networking equipment requires industry-leading knowledge-based processors that can perform Layers 2-4 network processing such as classification, security and forwarding at higher speeds while supporting a 4x increase in Internet protocol address widths.
The NL82048 knowledge-based processor incorporates a number of ground-breaking innovations, and is the first device in the industry that is capable of supporting up to 512,000 IPv6 addresses or 2,000,000 IPv4 addresses. The NL82048 knowledge-based processor integrates 256 high-performance knowledge-based processing engines, and supports a daisy-chain clustering scheme that enables customers to quadruple the number of IPv6 addresses without impacting line rate.
The NL82048 knowledge-based processor also supports more than a million Quality-of-Service (QoS) or Access Control List (ACL) entries, which is four times the number of entries compared with any other device addressing the similar target market. This extends NetLogic Microsystems’ technology and market leadership in knowledge-based processing, and enables NetLogic Microsystems to optimally address the processing requirements of even the most feature rich networking systems.
In addition, the NL82048 incorporates advanced clock switching schemes to achieve an aggregate interface bandwidth of 80 gigabits per second and can perform up to 1.2 billion decisions per second. This capability to execute multiple parallel decisions during a single core clock cycle combined with our highly pipelined synchronous cross-connect bussing scheme enables customers to deploy 100 Gbps ASICs, switches, and network processors.
“We are pleased to have the industry’s most comprehensive portfolio of IPv6 knowledge-based processors,” said Chris O’Reilly, vice president of marketing at NetLogic Microsystems. “By integrating key innovations that dramatically enhances the performance and enriches the feature set of our market-leading knowledge-based processors, we continue to enable our customers to develop highly differentiated networking solutions for next-generation LTE networks.”
Sample orders of the NL82048 are now being accepted with standard lead times.
The exponential growth in the number of connected mobile devices, services and applications for next-generation LTE deployments are driving the global migration from IPv4 to IPv6 network architectures.
In order to support this migration to IPv6, as well as the continued increases in complexity and higher throughputs of network traffic, next-generation networking equipment requires industry-leading knowledge-based processors that can perform Layers 2-4 network processing such as classification, security and forwarding at higher speeds while supporting a 4x increase in Internet protocol address widths.
The NL82048 knowledge-based processor incorporates a number of ground-breaking innovations, and is the first device in the industry that is capable of supporting up to 512,000 IPv6 addresses or 2,000,000 IPv4 addresses. The NL82048 knowledge-based processor integrates 256 high-performance knowledge-based processing engines, and supports a daisy-chain clustering scheme that enables customers to quadruple the number of IPv6 addresses without impacting line rate.
The NL82048 knowledge-based processor also supports more than a million Quality-of-Service (QoS) or Access Control List (ACL) entries, which is four times the number of entries compared with any other device addressing the similar target market. This extends NetLogic Microsystems’ technology and market leadership in knowledge-based processing, and enables NetLogic Microsystems to optimally address the processing requirements of even the most feature rich networking systems.
In addition, the NL82048 incorporates advanced clock switching schemes to achieve an aggregate interface bandwidth of 80 gigabits per second and can perform up to 1.2 billion decisions per second. This capability to execute multiple parallel decisions during a single core clock cycle combined with our highly pipelined synchronous cross-connect bussing scheme enables customers to deploy 100 Gbps ASICs, switches, and network processors.
“We are pleased to have the industry’s most comprehensive portfolio of IPv6 knowledge-based processors,” said Chris O’Reilly, vice president of marketing at NetLogic Microsystems. “By integrating key innovations that dramatically enhances the performance and enriches the feature set of our market-leading knowledge-based processors, we continue to enable our customers to develop highly differentiated networking solutions for next-generation LTE networks.”
Sample orders of the NL82048 are now being accepted with standard lead times.
GigaChip Alliance adds Xilinx to its roster and launches website
DesignCon 2011, SANTA CLARA, USA: MoSys Inc., a leading architect of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, announced that Xilinx Inc. has joined the GigaChip Alliance, an ecosystem of companies that support the GigaChip Interface.
Current alliance participants include: MoSys, Altera Corp., NetLogic Microsystems and Xilinx. In addition, MoSys announced the launch of the GigaChip Alliance website, which provides information regarding the GigaChip Interface and the GigaChip Alliance.
The GigaChip Interface is a short-reach, low-power serial interface, which enables highly efficient, high-bandwidth, low-latency performance not achievable using currently available serial protocols. Similar to the fundamental performance breakthrough achieved by the move to double data rate (DDR) style interfaces in the late ‘90s, MoSys believes the GigaChip Interface represents the next breakthrough in chip-to-chip communications using differential SerDes technology.
A 16-lane GigaChip Interface can replace up to six separate DDR3 parallel interface busses to memory, which represents a bandwidth density performance increase of four times, while reducing system power and interface costs by two to three times. Such bandwidth density increases will be required to realize line cards with aggregate throughput beyond 100G, a necessity in future high-end networking systems.
The GigaChip Interface has adopted the open CEI-11 electrical transport standard, making use of this existing electrical ecosystem in order to shorten time to market for the introduction of next generation system designs. Through the GigaChip Alliance, companies are enabling an entirely new class of low-cost, high-speed, high-performance systems in networking, computing and storage markets.
“As the world’s leading provider of programmable solutions, we are pleased to join the GigaChip Alliance and plan to support the GigaChip Interface in our FPGAs,” said Sanjay Charagulla, director, Corporate Strategic Planning at Xilinx. "We see a major trend towards serial chip-to-chip communications and believe the GigaChip Interface provides the efficiency and openness that our customers require."
"We couldn't be more pleased to have Xilinx join the GigaChip Alliance to support the proliferation of the GigaChip Interface into next generation networking systems,” stated David DeMaria, VP of Business Operations for MoSys. “Our goal is to revolutionize serial chip-to-chip communications with the GigaChip Interface. Towards that end, we are making the GigaChip Interface an open protocol and encouraging widespread use by potential partners and customers. The GigaChip Alliance will facilitate industry-wide adoption and evolution of this protocol.”
At the DesignCon 2011 conference being held from January 31 to February 3 at the Santa Clara Convention Center, MoSys and Xilinx will be demonstrating interoperability between the MoSys Bandwidth Engine IC and Xilinx FPGAs using the GigaChip Interface. Demonstrations will be held at MoSys’ booth 516 on February 2 and 3 during the expo portion of the conference.
Current alliance participants include: MoSys, Altera Corp., NetLogic Microsystems and Xilinx. In addition, MoSys announced the launch of the GigaChip Alliance website, which provides information regarding the GigaChip Interface and the GigaChip Alliance.
The GigaChip Interface is a short-reach, low-power serial interface, which enables highly efficient, high-bandwidth, low-latency performance not achievable using currently available serial protocols. Similar to the fundamental performance breakthrough achieved by the move to double data rate (DDR) style interfaces in the late ‘90s, MoSys believes the GigaChip Interface represents the next breakthrough in chip-to-chip communications using differential SerDes technology.
A 16-lane GigaChip Interface can replace up to six separate DDR3 parallel interface busses to memory, which represents a bandwidth density performance increase of four times, while reducing system power and interface costs by two to three times. Such bandwidth density increases will be required to realize line cards with aggregate throughput beyond 100G, a necessity in future high-end networking systems.
The GigaChip Interface has adopted the open CEI-11 electrical transport standard, making use of this existing electrical ecosystem in order to shorten time to market for the introduction of next generation system designs. Through the GigaChip Alliance, companies are enabling an entirely new class of low-cost, high-speed, high-performance systems in networking, computing and storage markets.
“As the world’s leading provider of programmable solutions, we are pleased to join the GigaChip Alliance and plan to support the GigaChip Interface in our FPGAs,” said Sanjay Charagulla, director, Corporate Strategic Planning at Xilinx. "We see a major trend towards serial chip-to-chip communications and believe the GigaChip Interface provides the efficiency and openness that our customers require."
"We couldn't be more pleased to have Xilinx join the GigaChip Alliance to support the proliferation of the GigaChip Interface into next generation networking systems,” stated David DeMaria, VP of Business Operations for MoSys. “Our goal is to revolutionize serial chip-to-chip communications with the GigaChip Interface. Towards that end, we are making the GigaChip Interface an open protocol and encouraging widespread use by potential partners and customers. The GigaChip Alliance will facilitate industry-wide adoption and evolution of this protocol.”
At the DesignCon 2011 conference being held from January 31 to February 3 at the Santa Clara Convention Center, MoSys and Xilinx will be demonstrating interoperability between the MoSys Bandwidth Engine IC and Xilinx FPGAs using the GigaChip Interface. Demonstrations will be held at MoSys’ booth 516 on February 2 and 3 during the expo portion of the conference.
IDT intros industry’s first single-layer multi-touch capacitive touch screen controller
SAN JOSE, USA: Integrated Device Technology Inc. (IDT) has announced the industry’s first touch screen controller IC optimized for IDT’s proprietary single-layer multi-touch projected capacitive touch screen technology.
This new touch screen technology and controller solution revolutionizes the market by offering a true single-layer solution, not requiring cross-over isolation points that other solutions require, yet still maintaining full multi-touch capability. The result is a lower-cost total solution that does not sacrifice features or performance. Typical applications include mobile handsets, personal navigation devices, and handheld gaming platforms with screen sizes up to five inches.
The IDT LDS7000 and LDS7001 are high-performance, multi-touch, full resolution touch screen controller ICs featuring up to 30 and 35 sensor channels, respectively. Both controllers operate at a speedy 8ms data rate for quick response to touch inputs to improve the user’s experience and enable advanced applications that require fast response times.
The IDT LDS7000 family’s proprietary algorithms eliminate undesired multi touch ghosting, providing accurate individual X and Y coordinates in dual touch mode, a critical requirement for customers using host-interpreted custom gestures to differentiate their end product. The devices’ analog front-end design provides a high level of noise rejection performance that negates the need for a separate touch screen shield layer for most applications, lowering the overall solution cost even further.
“The new LDS7000 family of touch controllers enables our customers to take full advantage of IDT’s true single-layer touch screen technology,” said Alvin Wong, general manager of the Advanced User Interface group at IDT.
“Our innovative design and multi-touch capabilities allow touch screen manufacturers to simplify their manufacturing processes, yet maintain the critical feature set that is required for today’s most advanced consumer devices. IDT continues to extend its presence in breakthrough capacitive touch technologies and designs that improve the user experience, so our customers can deliver winning products to the market.”
“The market for multi-touch capable controllers continues to expand based on increasing adoption rates across the globe of smartphones, and since 2010, an exploding market for media tablet PCs, “ said Randy Lawson, Principal Analyst, Display Electronics at iSuppli.
“As screen resolutions and application processor data rates continue to climb in these applications, the ability to discern and reject injected noise at the controller has become a more compelling feature for device manufacturers when selecting their touch screen controller IC provider.”
The IDT LDS7000 and LDS7001 devices offer native support for a 10-bit resolution (1024 x 1024) with the ability to scale the touch values of the X and Y axes, offering the flexibility to apply this solution to different resolution LCD and AMOLED panels. In addition, the single-layer solution offers improved backlight transmittance, while the devices’ low power modes maximize battery life in portable electronics.
The IDT LDS7000 is currently sampling to qualified customers and is available in a 5x5 mm, 40-pin TQFN package. It is priced at $2.50 in 10,000-unit quantities. The IDT LDS7001 is currently sampling to qualified customers and is available in a 6x6 mm, 48-pin TQFN package. It is priced at $2.95 in 10,000-unit quantities.
This new touch screen technology and controller solution revolutionizes the market by offering a true single-layer solution, not requiring cross-over isolation points that other solutions require, yet still maintaining full multi-touch capability. The result is a lower-cost total solution that does not sacrifice features or performance. Typical applications include mobile handsets, personal navigation devices, and handheld gaming platforms with screen sizes up to five inches.
The IDT LDS7000 and LDS7001 are high-performance, multi-touch, full resolution touch screen controller ICs featuring up to 30 and 35 sensor channels, respectively. Both controllers operate at a speedy 8ms data rate for quick response to touch inputs to improve the user’s experience and enable advanced applications that require fast response times.
The IDT LDS7000 family’s proprietary algorithms eliminate undesired multi touch ghosting, providing accurate individual X and Y coordinates in dual touch mode, a critical requirement for customers using host-interpreted custom gestures to differentiate their end product. The devices’ analog front-end design provides a high level of noise rejection performance that negates the need for a separate touch screen shield layer for most applications, lowering the overall solution cost even further.
“The new LDS7000 family of touch controllers enables our customers to take full advantage of IDT’s true single-layer touch screen technology,” said Alvin Wong, general manager of the Advanced User Interface group at IDT.
“Our innovative design and multi-touch capabilities allow touch screen manufacturers to simplify their manufacturing processes, yet maintain the critical feature set that is required for today’s most advanced consumer devices. IDT continues to extend its presence in breakthrough capacitive touch technologies and designs that improve the user experience, so our customers can deliver winning products to the market.”
“The market for multi-touch capable controllers continues to expand based on increasing adoption rates across the globe of smartphones, and since 2010, an exploding market for media tablet PCs, “ said Randy Lawson, Principal Analyst, Display Electronics at iSuppli.
“As screen resolutions and application processor data rates continue to climb in these applications, the ability to discern and reject injected noise at the controller has become a more compelling feature for device manufacturers when selecting their touch screen controller IC provider.”
The IDT LDS7000 and LDS7001 devices offer native support for a 10-bit resolution (1024 x 1024) with the ability to scale the touch values of the X and Y axes, offering the flexibility to apply this solution to different resolution LCD and AMOLED panels. In addition, the single-layer solution offers improved backlight transmittance, while the devices’ low power modes maximize battery life in portable electronics.
The IDT LDS7000 is currently sampling to qualified customers and is available in a 5x5 mm, 40-pin TQFN package. It is priced at $2.50 in 10,000-unit quantities. The IDT LDS7001 is currently sampling to qualified customers and is available in a 6x6 mm, 48-pin TQFN package. It is priced at $2.95 in 10,000-unit quantities.
Speculative buying in Chinese market triggered 20 percent increase in DDR3 2GB spot price
TAIWAN: According to DRAMeXchange, a research department of Trendforce, DDR3 1333 MHz 2Gb spot price surged from $1.83 to $2.03 before closing on Jan. 27th. Second day in Asia, the midday price arrived at $2.24, an impressive accumulated 22 percent increase in two days. On the other hand, DDR3 1333 MHz 1Gb raised 12 percent to $1.18.
The DDR3 spot price in 1Q10 remains relatively high. On April 22nd, 2010, DDR3 1Gb 1333MHz were dealt at $3.02. However, the average price had fallen below $2 on October 12th, 2010 and reached the bottom, $1.05, on January 26th, 2011.
Overall, the DDR3 spot price has accumulatively declined 66 percent from the peak. More specifically, DDR3 2Gb 1333 MHz spot price has dropped from $4.85 to $1.76, a 66 percent price decline over the five month period. The spot price decline seems eased and reached its bottom in January, 2011.
With the upcoming Chinese New Year, Asian spot market included Hong Kong, Taiwan, and Korea will be closed in early February. The need to replenish inventory from the Chinese market has shown a slightly upward trend in spot price on the 25th and the 26th. The indicator of rebound has triggered speculative buying while and provided incentive for vendors to hold on to a portion of their inventories. Thus, this phenomenon leads to a two day 20 percent rocketed climbing in DDR3 2Gb spot price.
The momentum is very strong, we are expecting to see some price fluctuation after the Chinese New Year, but overall price will be going in a steady upward trend.
DRAM contract price is also reaching its bottom, a 20-25 percent increase is expected in 2Q11.
Expecting an explosive growth in Smartphone and tablet PC, and an increasing demand for servers utilized in cloud computing, DRAM vendors have planned to move their capacity to mobile DRAM, server DRAM and foundry business from commodity DRAM.
Commodity DRAM is considered high-risk, because its volatility in price. 2011 DRAM content per box growth is expected to be 30 percent with the launch of Intel Sandy Bridge. DRAM content will be increased from 3GB to 4GB. DRAMeXchange expects as PC OEMs start to replenish their inventory in April DDR3 contract price will increase 20 to 25 percent in second quarter.
The DDR3 spot price in 1Q10 remains relatively high. On April 22nd, 2010, DDR3 1Gb 1333MHz were dealt at $3.02. However, the average price had fallen below $2 on October 12th, 2010 and reached the bottom, $1.05, on January 26th, 2011.
Overall, the DDR3 spot price has accumulatively declined 66 percent from the peak. More specifically, DDR3 2Gb 1333 MHz spot price has dropped from $4.85 to $1.76, a 66 percent price decline over the five month period. The spot price decline seems eased and reached its bottom in January, 2011.
With the upcoming Chinese New Year, Asian spot market included Hong Kong, Taiwan, and Korea will be closed in early February. The need to replenish inventory from the Chinese market has shown a slightly upward trend in spot price on the 25th and the 26th. The indicator of rebound has triggered speculative buying while and provided incentive for vendors to hold on to a portion of their inventories. Thus, this phenomenon leads to a two day 20 percent rocketed climbing in DDR3 2Gb spot price.
The momentum is very strong, we are expecting to see some price fluctuation after the Chinese New Year, but overall price will be going in a steady upward trend.
DRAM contract price is also reaching its bottom, a 20-25 percent increase is expected in 2Q11.
Expecting an explosive growth in Smartphone and tablet PC, and an increasing demand for servers utilized in cloud computing, DRAM vendors have planned to move their capacity to mobile DRAM, server DRAM and foundry business from commodity DRAM.
Commodity DRAM is considered high-risk, because its volatility in price. 2011 DRAM content per box growth is expected to be 30 percent with the launch of Intel Sandy Bridge. DRAM content will be increased from 3GB to 4GB. DRAMeXchange expects as PC OEMs start to replenish their inventory in April DDR3 contract price will increase 20 to 25 percent in second quarter.
Yissum and Vaxan to collaborate for development of novel nanoparticle ink for printed electronics
JERUSALEM: Yissum Research Development Co. Ltd, the Technology Transfer Company of the Hebrew University of Jerusalem, and Vaxan Steel Co. Ltd., a leading Korean company in the field of innovative printing, signed a licensing and research agreement for the development of silver nanoparticles and silver-coated copper nanoparticles for conductive inks.
These inks can be utilized in a variety of printing technologies, including inkjet printing. The novel conductive inks were invented by Professor Shlomo Magdassi, Dr. Alexander Kamyshny and Michael Grouchko from the Institute of Chemistry at the Hebrew University.
According to the terms of the agreement, Yissum grants Vaxan a license to commercialize the technology exclusively in Asia, excluding Israel and former Soviet Union countries, and will receive in return research fees and royalties from future sales.
One of the exciting fields of the present and near future is printed electronics – the ability to print electric circuits on almost any surface, including paper, plastic, silicon and ceramics. Printed electronics are in use, or are considered for use in multiple applications, including displays and thin-film photovoltaics, radio frequency identification (RFID) tags, OLED lighting and sensors.
Conducting printing for the electronics industry is traditionally achieved by lithography and screen printing technologies. However, these methods are usually time consuming and expensive. Therefore, during recent years the printing electronics industry trends towards digital printing, with inkjet printing as the most appealing technology. In this printing technology, droplets of ink containing metallic nanoparticles are jetted from a micron size orifice, onto the substrate which can be a plastic sheet, a glass or a silicon wafer.
Silver nanoparticles are particularly appealing for inkjet printing, since silver is the most conductive of the metals, and in contrast to other metals, oxidation does not harm the conductivity of the final film. For this reason, silver was the first material used for inks and conductive printing on a wide scale. Copper, on the other hand, is much cheaper than silver (at about 1/100 the cost of silver), but is readily oxidized by air, thereby becoming non-conductive.
Prof. Magdassi and his colleagues invented copper nanoparticles that are covered by a thin layer of silver, thereby producing cheap, conductive, air-stable particles that can be readily used as conductive ink for a variety of applications.
"We are proud that the Hebrew University has had the opportunity to take part in this collaboration, and hope to strengthen our ties with the Korean industry in the future," said Yaacov Michlin, CEO of Yissum. "We are confident that our new partners will help us in introducing this invention to the market."
Duek Chi Lee, CEO of VAXAN, said: "The nanotechnology application which we have licensed from Yissum will be applied to semiconductors, IT, LED, and OLED industries. We are certain that this technological innovation will be an international success in electronic markets of the future. Once again, I would like to thank Yissum, Prof. Magdassi and GlobalTech Korea who helped promote this collaboration between Korea and Israel."
Hyunsung Kim, from GlobalTech Korea, said: "We are very excited with this agreement, which marks the first commercial collaboration between an Israeli university and a Korean company. We at GlobalTech Korea's Tel Aviv office will continue to do our best to advance future R&D collaboration between the two countries."
These inks can be utilized in a variety of printing technologies, including inkjet printing. The novel conductive inks were invented by Professor Shlomo Magdassi, Dr. Alexander Kamyshny and Michael Grouchko from the Institute of Chemistry at the Hebrew University.
According to the terms of the agreement, Yissum grants Vaxan a license to commercialize the technology exclusively in Asia, excluding Israel and former Soviet Union countries, and will receive in return research fees and royalties from future sales.
One of the exciting fields of the present and near future is printed electronics – the ability to print electric circuits on almost any surface, including paper, plastic, silicon and ceramics. Printed electronics are in use, or are considered for use in multiple applications, including displays and thin-film photovoltaics, radio frequency identification (RFID) tags, OLED lighting and sensors.
Conducting printing for the electronics industry is traditionally achieved by lithography and screen printing technologies. However, these methods are usually time consuming and expensive. Therefore, during recent years the printing electronics industry trends towards digital printing, with inkjet printing as the most appealing technology. In this printing technology, droplets of ink containing metallic nanoparticles are jetted from a micron size orifice, onto the substrate which can be a plastic sheet, a glass or a silicon wafer.
Silver nanoparticles are particularly appealing for inkjet printing, since silver is the most conductive of the metals, and in contrast to other metals, oxidation does not harm the conductivity of the final film. For this reason, silver was the first material used for inks and conductive printing on a wide scale. Copper, on the other hand, is much cheaper than silver (at about 1/100 the cost of silver), but is readily oxidized by air, thereby becoming non-conductive.
Prof. Magdassi and his colleagues invented copper nanoparticles that are covered by a thin layer of silver, thereby producing cheap, conductive, air-stable particles that can be readily used as conductive ink for a variety of applications.
"We are proud that the Hebrew University has had the opportunity to take part in this collaboration, and hope to strengthen our ties with the Korean industry in the future," said Yaacov Michlin, CEO of Yissum. "We are confident that our new partners will help us in introducing this invention to the market."
Duek Chi Lee, CEO of VAXAN, said: "The nanotechnology application which we have licensed from Yissum will be applied to semiconductors, IT, LED, and OLED industries. We are certain that this technological innovation will be an international success in electronic markets of the future. Once again, I would like to thank Yissum, Prof. Magdassi and GlobalTech Korea who helped promote this collaboration between Korea and Israel."
Hyunsung Kim, from GlobalTech Korea, said: "We are very excited with this agreement, which marks the first commercial collaboration between an Israeli university and a Korean company. We at GlobalTech Korea's Tel Aviv office will continue to do our best to advance future R&D collaboration between the two countries."
Wind River, Magneti Marelli to deliver first-of-its-kind GENIVI in-vehicle infotainment solution for automotive industry
BANGALORE, INDIA: Wind River, a leader in embedded and mobile software, and Magneti Marelli, a global automotive high-tech systems and component supplier, has announced a technological collaboration to create the first GENIVI-compliant in-vehicle infotainment (IVI) solution for the automotive industry.
Leading the development of the IVI solution, Magneti Marelli leveraged its extensive automotive know-how in integrating complex systems and technologies for the vehicle environment. Wind River provided an integrated, tested and validated IVI software platform based on the GENIVI open source standard, as well as customization and consulting services.
“GENIVI provides an innovative platform that allows car manufacturers to offer the next generation of connectivity and multimedia services while retaining the distinguishing features that make up the essence of their brands,” said Alexander Kocher, vice president and general manger for automotive solutions at Wind River. “Starting with BMW, Wind River and Magneti Marelli are providing car manufacturers with an IVI solution, delivering the latest infotainment technologies via open source software, which promotes the acceleration of innovation while reducing time-to-market and development costs.”
“The open platform approach can be considered the basis on which the future of in-vehicle life and infotainment will be built,” said Giuseppe Faranda, director of the infotainment and navigation division at Magneti Marelli. “Magneti Marelli’s history, experience and know-how in automotive electronics and systems integration naturally match this approach.”
Magneti Marelli and Wind River have partnered to deliver a reference platform for in-vehicle infotainment, compliant with the emerging GENIVI industry standard. The GENIVI open source platform standard aims to provide automobile manufacturers and their suppliers a common underlying framework to simplify elements of the in-vehicle infotainment development process that have historically been duplicated across the industry.
The new IVI solution, which is compliant with the GENIVI standard, can support a range of control module or “head unit” architectures and is available and customizable for all car manufacturers. Open source software creates a compelling option for Tier 1 suppliers to use as a foundation for IVI devices because it provides greater flexibility and opportunities for innovation, especially in the areas of advanced in-vehicle information, entertainment and connectivity. It also enables sophisticated navigation, telematic and multimedia devices inside automobiles.
The IVI solution will first appear as next-generation entry and mid level IVI systems for BMW Group vehicles.
Wind River and Magneti Marelli will continue to work together to maintain and evolve the Linux reference platform as the basis for future product developments.
Leading the development of the IVI solution, Magneti Marelli leveraged its extensive automotive know-how in integrating complex systems and technologies for the vehicle environment. Wind River provided an integrated, tested and validated IVI software platform based on the GENIVI open source standard, as well as customization and consulting services.
“GENIVI provides an innovative platform that allows car manufacturers to offer the next generation of connectivity and multimedia services while retaining the distinguishing features that make up the essence of their brands,” said Alexander Kocher, vice president and general manger for automotive solutions at Wind River. “Starting with BMW, Wind River and Magneti Marelli are providing car manufacturers with an IVI solution, delivering the latest infotainment technologies via open source software, which promotes the acceleration of innovation while reducing time-to-market and development costs.”
“The open platform approach can be considered the basis on which the future of in-vehicle life and infotainment will be built,” said Giuseppe Faranda, director of the infotainment and navigation division at Magneti Marelli. “Magneti Marelli’s history, experience and know-how in automotive electronics and systems integration naturally match this approach.”
Magneti Marelli and Wind River have partnered to deliver a reference platform for in-vehicle infotainment, compliant with the emerging GENIVI industry standard. The GENIVI open source platform standard aims to provide automobile manufacturers and their suppliers a common underlying framework to simplify elements of the in-vehicle infotainment development process that have historically been duplicated across the industry.
The new IVI solution, which is compliant with the GENIVI standard, can support a range of control module or “head unit” architectures and is available and customizable for all car manufacturers. Open source software creates a compelling option for Tier 1 suppliers to use as a foundation for IVI devices because it provides greater flexibility and opportunities for innovation, especially in the areas of advanced in-vehicle information, entertainment and connectivity. It also enables sophisticated navigation, telematic and multimedia devices inside automobiles.
The IVI solution will first appear as next-generation entry and mid level IVI systems for BMW Group vehicles.
Wind River and Magneti Marelli will continue to work together to maintain and evolve the Linux reference platform as the basis for future product developments.
LDRA delivers assembler level support for MIPS processors
WIRRAL, UK: LDRA, the leading provider of automated software verification, source code analysis and test tools now supports assembly-level code for MIPS processors.
Targeting high reliability applications in aviation, satellite, medical and aerospace, the LDRA tool suite provides assembler support for Green Hills and GNU variants of MIPS assembly along with C-style macro syntax. Thanks to this support, legacy applications can be fully certified to the most rigorous levels of DO-178B and FDA certification.
Legacy applications frequently lack source code, making it impossible to provide source–to–object-code traceability that verifies that no code can trigger unexpected or errant behaviour when the application executes. With LDRA assembler support, applications lacking source code can be disassembled into object code that boasts the complete range of artifacts needed for certification. Reports can then link source and object code, fulfilling the structural coverage analysis of certifications such as DO-178B.
With a unique ability to process instructions simultaneously, MIPS processors deliver very large I/O throughput and fast processing capabilities with minimal power and weight, making them ideal for the computationally intensive aerospace environment.
To ensure complete code coverage, LDRA’s tool suite accounts for the MIPS processor's ability to execute multiple instructions simultaneously and predicatively execute instructions down the pipeline. The LDRA tool suite accurately records coverage information, ensuring that any code optimized for the MIPS architecture is fully accounted for.
“The MIPS architecture with its unique execution capabilities offers high-end applications additional processing power,” noted Ian Hennell, LDRA Operations Director. “Thanks to LDRA assembler support, legacy applications on the MIPS architecture can meet new certification standards, even though they may lack full high-level code, involve hand-coded assembly, or contain board-specific BIOS code that previously could not be certified. With this integration, the LDRA tool suite delivers the necessary artifacts to certify these legacy applications, saving companies the development and cost of writing, testing and verifying new code.”
LDRA tool suite for MIPS assembler code enables the certification of BIOS and board-level support as well as hand-coded assembly for all MIPS processors including those environmentally hardened. The LDRA tool suite for assembly code provides the full range of verification artifacts needed for mission- or safety-critical certification. In addition, the DO-178B Tool Qualification Support Package for Object Code Verification provides complete source–to–object-code traceability for customer-specified environments.
Targeting high reliability applications in aviation, satellite, medical and aerospace, the LDRA tool suite provides assembler support for Green Hills and GNU variants of MIPS assembly along with C-style macro syntax. Thanks to this support, legacy applications can be fully certified to the most rigorous levels of DO-178B and FDA certification.
Legacy applications frequently lack source code, making it impossible to provide source–to–object-code traceability that verifies that no code can trigger unexpected or errant behaviour when the application executes. With LDRA assembler support, applications lacking source code can be disassembled into object code that boasts the complete range of artifacts needed for certification. Reports can then link source and object code, fulfilling the structural coverage analysis of certifications such as DO-178B.
With a unique ability to process instructions simultaneously, MIPS processors deliver very large I/O throughput and fast processing capabilities with minimal power and weight, making them ideal for the computationally intensive aerospace environment.
To ensure complete code coverage, LDRA’s tool suite accounts for the MIPS processor's ability to execute multiple instructions simultaneously and predicatively execute instructions down the pipeline. The LDRA tool suite accurately records coverage information, ensuring that any code optimized for the MIPS architecture is fully accounted for.
“The MIPS architecture with its unique execution capabilities offers high-end applications additional processing power,” noted Ian Hennell, LDRA Operations Director. “Thanks to LDRA assembler support, legacy applications on the MIPS architecture can meet new certification standards, even though they may lack full high-level code, involve hand-coded assembly, or contain board-specific BIOS code that previously could not be certified. With this integration, the LDRA tool suite delivers the necessary artifacts to certify these legacy applications, saving companies the development and cost of writing, testing and verifying new code.”
LDRA tool suite for MIPS assembler code enables the certification of BIOS and board-level support as well as hand-coded assembly for all MIPS processors including those environmentally hardened. The LDRA tool suite for assembly code provides the full range of verification artifacts needed for mission- or safety-critical certification. In addition, the DO-178B Tool Qualification Support Package for Object Code Verification provides complete source–to–object-code traceability for customer-specified environments.
Synopsys and Jawaharlal Nehru Technological University (JNTU) Hyderabad establish microelectronics program
HYDERABAD, INDIA: Synopsys Inc. and Jawaharlal Nehru Technological University (JNTU) Hyderabad have signed a long-term cooperation agreement establishing a Microelectronics program in VLSI Engineering at JNTU Hyderabad.
The program is aimed at training local talent and providing highly skilled specialists that can address the complex design requirements of semiconductor industry companies. Training skilled specialists in electronics is a key factor in the competiveness of India’s high-tech economy.
The plan is for the newly established Bachelors and Masters Programs in JNTU Hyderabad to provide skill development opportunities to more than 300,000 students every year. JNTU Hyderabad is the largest nodal university in India, with more than 300 affiliated colleges. The program is designed to educate students in integrated circuit design and automation based on tools and customized curriculum offered through the Synopsys University Program.
Using a proven educational model of industry-academia cooperation, the program is expected to provide India’s workforce with graduates who have the knowledge and skills required to be quickly productive in the industry, and who can help lead India into the next stage of technology development.
Under the program, Synopsys plans to donate to JNTU Hyderabad a state-of-the-art educational environment that gives university students access to:
* Synopsys’ comprehensive, industry-leading analog, digital and embedded electronic design automation (EDA) software, including Educational Design Kit (EDK) and interoperable Process Design Kit (iPDK);
* Customized curricula developed by the Synopsys Armenia Education Department as part of the Synopsys Worldwide University Program; and
* Guidance in implementing the Bachelors and Masters programs.
Synopsys also plans to support the program by offering experienced Synopsys or Synopsys-trained personnel skilled in conducting electronic design automation training and development.
“The huge promise that India holds for the growth of the high tech electronics systems industry depends to a large extent on the availability of qualified, industry-ready, VLSI trained engineers,” said Dr. Pradip Dutta, corporate VP and MD, Synopsys India. “This industry-academia collaboration with JNTU Hyderabad will provide a great opportunity to bring skilled resources to the industry from the one of the largest engineering student communities in India.”
“The Synopsys University Program provides unique value in microelectronics education,” said Rich Goldman, vice president of Corporate Marketing and Strategic Alliances at Synopsys. “This collaboration between industry and university has enabled a program that develops graduates who are ready to be productive in the workforce and who know they have received a world-class education that is current with the fast-moving semiconductor industry. I look forward to extending this program in India in cooperation with JNTU Hyderabad.”
“JNTU Hyderabad is pleased to receive this unique honour,” said Vice-Chancellor Prof. D. Narasimha Reddy at JNTU Hyderabad. “We thank Synopsys for this generous donation and Seer Akademi for advocating our cause. JNTU Hyderabad’s collaboration with Synopsys and Seer Akademi will result in a new generation of highly skilled industry ready graduates and professors.”
“The shortage of skilled engineers in the Indian semiconductor industry can be addressed effectively and efficiently only by a close collaboration among universities and industry,” said Anil Gupta, CEO of Metalogic Circuits, and a member of the Board of Studies at JNTU. “As an alumnus of JNTU, I am very proud to see Synopsys selecting my alma mater for this important initiative.”
Gupta has first-hand knowledge of the difficulties associated with hiring skilled engineers. He was managing director of Infineon India and ARM India, before he launched his own enterprise.
JNTU Hyderabad will use the instructional services from Seer Akademi, a curriculum partner and member of the Synopsys University Program, to effectively administer the Synopsys curriculum and to ensure effective use.
“The collaboration among Synopsys, Seer Akademi and JNTU Hyderabad has resulted in a pioneering program that can be the reference model for all technical education in India and in other developing knowledge-based economies,” said Srikanth Jadcherla, chairman and CEO of Seer Akademi. “We congratulate and thank Synopsys for its generous donation to help thousands of Indian students acquire industry-ready skills.”
The program is aimed at training local talent and providing highly skilled specialists that can address the complex design requirements of semiconductor industry companies. Training skilled specialists in electronics is a key factor in the competiveness of India’s high-tech economy.
The plan is for the newly established Bachelors and Masters Programs in JNTU Hyderabad to provide skill development opportunities to more than 300,000 students every year. JNTU Hyderabad is the largest nodal university in India, with more than 300 affiliated colleges. The program is designed to educate students in integrated circuit design and automation based on tools and customized curriculum offered through the Synopsys University Program.
Using a proven educational model of industry-academia cooperation, the program is expected to provide India’s workforce with graduates who have the knowledge and skills required to be quickly productive in the industry, and who can help lead India into the next stage of technology development.
Under the program, Synopsys plans to donate to JNTU Hyderabad a state-of-the-art educational environment that gives university students access to:
* Synopsys’ comprehensive, industry-leading analog, digital and embedded electronic design automation (EDA) software, including Educational Design Kit (EDK) and interoperable Process Design Kit (iPDK);
* Customized curricula developed by the Synopsys Armenia Education Department as part of the Synopsys Worldwide University Program; and
* Guidance in implementing the Bachelors and Masters programs.
Synopsys also plans to support the program by offering experienced Synopsys or Synopsys-trained personnel skilled in conducting electronic design automation training and development.
“The huge promise that India holds for the growth of the high tech electronics systems industry depends to a large extent on the availability of qualified, industry-ready, VLSI trained engineers,” said Dr. Pradip Dutta, corporate VP and MD, Synopsys India. “This industry-academia collaboration with JNTU Hyderabad will provide a great opportunity to bring skilled resources to the industry from the one of the largest engineering student communities in India.”
“The Synopsys University Program provides unique value in microelectronics education,” said Rich Goldman, vice president of Corporate Marketing and Strategic Alliances at Synopsys. “This collaboration between industry and university has enabled a program that develops graduates who are ready to be productive in the workforce and who know they have received a world-class education that is current with the fast-moving semiconductor industry. I look forward to extending this program in India in cooperation with JNTU Hyderabad.”
“JNTU Hyderabad is pleased to receive this unique honour,” said Vice-Chancellor Prof. D. Narasimha Reddy at JNTU Hyderabad. “We thank Synopsys for this generous donation and Seer Akademi for advocating our cause. JNTU Hyderabad’s collaboration with Synopsys and Seer Akademi will result in a new generation of highly skilled industry ready graduates and professors.”
“The shortage of skilled engineers in the Indian semiconductor industry can be addressed effectively and efficiently only by a close collaboration among universities and industry,” said Anil Gupta, CEO of Metalogic Circuits, and a member of the Board of Studies at JNTU. “As an alumnus of JNTU, I am very proud to see Synopsys selecting my alma mater for this important initiative.”
Gupta has first-hand knowledge of the difficulties associated with hiring skilled engineers. He was managing director of Infineon India and ARM India, before he launched his own enterprise.
JNTU Hyderabad will use the instructional services from Seer Akademi, a curriculum partner and member of the Synopsys University Program, to effectively administer the Synopsys curriculum and to ensure effective use.
“The collaboration among Synopsys, Seer Akademi and JNTU Hyderabad has resulted in a pioneering program that can be the reference model for all technical education in India and in other developing knowledge-based economies,” said Srikanth Jadcherla, chairman and CEO of Seer Akademi. “We congratulate and thank Synopsys for its generous donation to help thousands of Indian students acquire industry-ready skills.”
10 Gbps repeaters from National Semiconductor double signal conditioning performance at half the power
HONG KONG: Extending its leadership in high-performance analog technology, National Semiconductor Corp. announced three multi-channel PowerWise 10 Gbps repeaters that provide the industry’s highest equalization gain (36 dB), consume half the power (55 mW/channel) and deliver twice the reach (20 meters over 24-AWG cable) of current industry solutions.
Powered by National’s third-generation SiGe BiCMOS process, National’s 10 Gbps repeater family extends interconnect reach and enables higher data bandwidth up to 10.3125 Gbps by performing both receive equalization and transmit de-emphasis to compensate for channel loss in data center and high-performance communication systems.
Target applications include high-speed active cable assemblies and FR-4 backplanes using serial protocols such as 10 GbE, Fibre Channel, XAUI, CPRI and Infiniband. The repeaters also support SAS/SATA out of band (OOB) signaling for storage applications.
The explosion of multimedia content on the Internet, cloud computing, and the advent of multi-core virtualized servers are pushing interface bandwidth requirements in modern data center systems. However, interconnect length remains the same, posing power and signal integrity issues. National’s signal conditioners embedded inside the active copper cable assemblies and backplane boards ensure signal integrity, reduce system power consumption and lower interconnect cost compared to optical alternatives.
National’s 10 Gbps repeaters enable these active copper solutions to consume 4x lower power and 2x longer reach than competitive cabling solutions through the use of a new SiGe BiCMOS process, which produces high bandwidth and low noise transistors that enable low jitter and ultra-low power. The quad DS100BR410 is well-suited for high density connectors such as QSFP and CXP, while the DS100BR111 is designed for single lane SFP+ connectors.
National’s 10 Gbps repeater family
The DS100BR410 includes four unidirectional channels and delivers 55 mW/channel typical power consumption, while supporting a 2.5V single-supply voltage. It extends interconnect reach by performing both receive equalization (up to 36 dB boost) and transmit de-emphasis (-9 dB) on each of its channels to compensate for channel loss. This allows for maximum flexibility in physical placement within a system.
The DS100BR210 with two unidirectional channels and the DS100BR111 with one bidirectional lane (one transmit, one receive channel) feature 65 mW per channel typical power consumption and support 3.3V and 2.5V supplies. Both devices perform receive equalization up to 36 dB gain and transmit de-emphasis of -12dB. All three repeaters allow powering down of unused channels, and apply signal conditioning settings via pin setting or SMBus (I2C compliant).
Powered by National’s third-generation SiGe BiCMOS process, National’s 10 Gbps repeater family extends interconnect reach and enables higher data bandwidth up to 10.3125 Gbps by performing both receive equalization and transmit de-emphasis to compensate for channel loss in data center and high-performance communication systems.
Target applications include high-speed active cable assemblies and FR-4 backplanes using serial protocols such as 10 GbE, Fibre Channel, XAUI, CPRI and Infiniband. The repeaters also support SAS/SATA out of band (OOB) signaling for storage applications.
The explosion of multimedia content on the Internet, cloud computing, and the advent of multi-core virtualized servers are pushing interface bandwidth requirements in modern data center systems. However, interconnect length remains the same, posing power and signal integrity issues. National’s signal conditioners embedded inside the active copper cable assemblies and backplane boards ensure signal integrity, reduce system power consumption and lower interconnect cost compared to optical alternatives.
National’s 10 Gbps repeaters enable these active copper solutions to consume 4x lower power and 2x longer reach than competitive cabling solutions through the use of a new SiGe BiCMOS process, which produces high bandwidth and low noise transistors that enable low jitter and ultra-low power. The quad DS100BR410 is well-suited for high density connectors such as QSFP and CXP, while the DS100BR111 is designed for single lane SFP+ connectors.
National’s 10 Gbps repeater family
The DS100BR410 includes four unidirectional channels and delivers 55 mW/channel typical power consumption, while supporting a 2.5V single-supply voltage. It extends interconnect reach by performing both receive equalization (up to 36 dB boost) and transmit de-emphasis (-9 dB) on each of its channels to compensate for channel loss. This allows for maximum flexibility in physical placement within a system.
The DS100BR210 with two unidirectional channels and the DS100BR111 with one bidirectional lane (one transmit, one receive channel) feature 65 mW per channel typical power consumption and support 3.3V and 2.5V supplies. Both devices perform receive equalization up to 36 dB gain and transmit de-emphasis of -12dB. All three repeaters allow powering down of unused channels, and apply signal conditioning settings via pin setting or SMBus (I2C compliant).
Jasper ActiveProp automates assertion-based verification for SoC design
MOUNTAIN VIEW, USA: Jasper Design Automation has introduced ActiveProp, an innovative new property synthesis tool that helps accelerate the adoption of assertion-based verification, including formal verification as well as simulation.
ActiveProp automatically generates high-level properties in industry-standard SystemVerilog Assertion (SVA) language, as well as human-readable reports, from RTL and simulation information. ActiveProp property synthesis helps expand the verification property set, increase functional coverage, and identify coverage holes, leading to higher-quality chip designs.
“ActiveProp delivers tremendous ROI by automating the creation of properties, producing high-quality results faster than ever thought possible,” said Kathryn Kranen, Jasper President and CEO. “Deploying ActiveProp standalone greatly improves verification efficiency for any assertion-based verification flow. It also has great synergy with Jasper formal solutions, to achieve faster proofs with JasperGold, and for design leverage with ActiveDesign.”
ActiveProp generates intelligent, high-quality properties (assertions, constraints and covers) automatically, and multiple simulation runs can further refine the intelligence of generated properties. Unique multi-cycle analysis contributes to property quality, and generates properties where the causal effects are far removed from the resulting effects, not just two or three cycles away. ActiveProp also handles hierarchy, extracting properties across different modules and levels of hierarchy.
The inputs to ActiveProp are RTL, simulation information and scoped signals of interest which the user can control. Any simulation or testbench, block, system-level, or full SoC, can be used as input. ActiveProp simulator input can be provided in two ways, either running ActiveProp on previously created simulation files, or linked during run time with the simulator. ActiveProp outputs industry-standard SVA properties, which are used in any assertion-based design and verification flow.
ActiveProp also features a number of pre-defined checks including static checks; checks for common design errors such as arithmetic overflow, bus conflicts and illegal clock-domain crossings; coverage checks for errors such as dead-end and unreachable states; and more.
ActiveProp is currently available.
ActiveProp automatically generates high-level properties in industry-standard SystemVerilog Assertion (SVA) language, as well as human-readable reports, from RTL and simulation information. ActiveProp property synthesis helps expand the verification property set, increase functional coverage, and identify coverage holes, leading to higher-quality chip designs.
“ActiveProp delivers tremendous ROI by automating the creation of properties, producing high-quality results faster than ever thought possible,” said Kathryn Kranen, Jasper President and CEO. “Deploying ActiveProp standalone greatly improves verification efficiency for any assertion-based verification flow. It also has great synergy with Jasper formal solutions, to achieve faster proofs with JasperGold, and for design leverage with ActiveDesign.”
ActiveProp generates intelligent, high-quality properties (assertions, constraints and covers) automatically, and multiple simulation runs can further refine the intelligence of generated properties. Unique multi-cycle analysis contributes to property quality, and generates properties where the causal effects are far removed from the resulting effects, not just two or three cycles away. ActiveProp also handles hierarchy, extracting properties across different modules and levels of hierarchy.
The inputs to ActiveProp are RTL, simulation information and scoped signals of interest which the user can control. Any simulation or testbench, block, system-level, or full SoC, can be used as input. ActiveProp simulator input can be provided in two ways, either running ActiveProp on previously created simulation files, or linked during run time with the simulator. ActiveProp outputs industry-standard SVA properties, which are used in any assertion-based design and verification flow.
ActiveProp also features a number of pre-defined checks including static checks; checks for common design errors such as arithmetic overflow, bus conflicts and illegal clock-domain crossings; coverage checks for errors such as dead-end and unreachable states; and more.
ActiveProp is currently available.
Saturday, January 29, 2011
CSR licences advanced ARM Cortex MPU technology
CAMBRIDGE, UK: ARM and CSR plc have signed a major licensing agreement for the ARM Cortex-A5 MPCore and Cortex-A9 MPCore multicore processors.
CSR intends to target the advanced technology towards strengthening its leadership position in providing location-aware SoC platforms for In-Vehicle Navigation and Infotainment and Portable Navigation Device (PND) markets and for new, emerging location-aware consumer device markets, especially in the fast growing economies of the BRIC (Brazil, Russia, India and China) countries.
"This licensing agreement expands our existing ARM processor portfolio, and is a clear demonstration of our commitment to enhance consumer experience with our platforms by investing in leading edge IP," said Kanwar Chadha, chief marketing officer, CSR. "We are now positioned to fully respond to market needs by exploiting the total potential of ARM powered system-on-chip solutions for next generation consumer devices and automotive systems."
"The scalability of both processors provides the flexibility for us to optimize the performance for each application within a low power footprint," added Babak Bastani, VP of Global Chip Design, CSR. "Combining our state of the art location and connectivity expertise with two software-compatible processors, based on the standard ARM architecture will enable us to reduce our development costs while delivering leading edge products to market in a timely manner."
"This latest agreement with a global leader in wireless connectivity and location markets demonstrates the continued market momentum for the ARM Cortex-A series processors and ARM MPCore technology," said Eric Schorn, VP marketing, Processor Division, ARM. "By leveraging the performance and power efficiency benefits of the Cortex family of processors along with their leading edge technologies, CSR can offer feature-rich, future proof solutions for every segment of the consumer electronics market."
The Cortex-A5 processor is fully application compatible with the Cortex-A9 processor, enabling joint access to an established developer and software ecosystem including Android, Adobe Flash, Java Platform Standard Edition (Java SE), JavaFX, Linux, Microsoft Windows Embedded, Symbian and Ubuntu, along with more than 700 ARM Connected Community members.
The ARM MPCore technology enables developers to exceed the performance of today's high-performance embedded devices while consuming significantly less power. In addition, the Cortex-A series processors feature power management features including adaptive gating, dynamic voltage and frequency scaling and the ability for each core to go independently into standby, dormant or power-off energy management states, providing control over the dynamic as well as the static energy consumed by both the processor and memories.
The Cortex-A5 and Cortex-A9 processors can contain up to four independently configured but fully coherent cores, carrying out multiple tasks on each one in parallel. However since any complexity is hidden in hardware, the processor can be programmed as easily as a single core processor by utilizing one of the many SMP-aware operating systems.
CSR intends to target the advanced technology towards strengthening its leadership position in providing location-aware SoC platforms for In-Vehicle Navigation and Infotainment and Portable Navigation Device (PND) markets and for new, emerging location-aware consumer device markets, especially in the fast growing economies of the BRIC (Brazil, Russia, India and China) countries.
"This licensing agreement expands our existing ARM processor portfolio, and is a clear demonstration of our commitment to enhance consumer experience with our platforms by investing in leading edge IP," said Kanwar Chadha, chief marketing officer, CSR. "We are now positioned to fully respond to market needs by exploiting the total potential of ARM powered system-on-chip solutions for next generation consumer devices and automotive systems."
"The scalability of both processors provides the flexibility for us to optimize the performance for each application within a low power footprint," added Babak Bastani, VP of Global Chip Design, CSR. "Combining our state of the art location and connectivity expertise with two software-compatible processors, based on the standard ARM architecture will enable us to reduce our development costs while delivering leading edge products to market in a timely manner."
"This latest agreement with a global leader in wireless connectivity and location markets demonstrates the continued market momentum for the ARM Cortex-A series processors and ARM MPCore technology," said Eric Schorn, VP marketing, Processor Division, ARM. "By leveraging the performance and power efficiency benefits of the Cortex family of processors along with their leading edge technologies, CSR can offer feature-rich, future proof solutions for every segment of the consumer electronics market."
The Cortex-A5 processor is fully application compatible with the Cortex-A9 processor, enabling joint access to an established developer and software ecosystem including Android, Adobe Flash, Java Platform Standard Edition (Java SE), JavaFX, Linux, Microsoft Windows Embedded, Symbian and Ubuntu, along with more than 700 ARM Connected Community members.
The ARM MPCore technology enables developers to exceed the performance of today's high-performance embedded devices while consuming significantly less power. In addition, the Cortex-A series processors feature power management features including adaptive gating, dynamic voltage and frequency scaling and the ability for each core to go independently into standby, dormant or power-off energy management states, providing control over the dynamic as well as the static energy consumed by both the processor and memories.
The Cortex-A5 and Cortex-A9 processors can contain up to four independently configured but fully coherent cores, carrying out multiple tasks on each one in parallel. However since any complexity is hidden in hardware, the processor can be programmed as easily as a single core processor by utilizing one of the many SMP-aware operating systems.
Accellera approves new version of electronic design system modeling standard
NAPA, USA: Accellera, an Electronic Design Automation (EDA) standards organization, announced that its Board of Directors approved a new version of Accellera's Standard Co-Emulation Modeling Interface (SCE-MI) specification as a new Accellera verification standard.
Version 2.1 speeds up electronic design verification since it allows a model developed for simulation to run in an emulation environment and vice versa. Version 2.1 has added support for a subset of the SystemVerilog Direct Programming Interface (DPI) and built a streaming, variable length messaging system on top of this, which reduces the number of synchronizations when compared to other available methodologies. Click here to download the standard.
"Accellera standards improve the electronic design experience for the semiconductor industry," remarked Shishpal Rawat, Accellera Chair. "We created this standard to alleviate one of the most critical bottlenecks in the electronic design cycle: verification. Given the reality of continually increasing design size and complexity, significant verification is enabled by SCE-MI as it allows simulation and emulation to be more interoperable."
"EDA suppliers are working to bring new SCE-MI 2.1 capabilities to their customers as quickly as possible, and our committee will continue to add features that address portability, performance and ease of use," said Brian Bailey, Interface Technical Committee (ITC) committee chair.
A previous version of the standard, SCE-MI 2.0, was approved by the Accellera Board in May 2007. The SCI-MI standard was first created and is being continually improved by Accellera's Interface Technical Committee (ITC).
The SCE-MI standard provides an easy way to connect and migrate transactor models between simulation, emulation and rapid prototyping environments. With it, design and verification teams can realize improved electronic design productivity. Model portability enhancements for transaction-level verification on heterogeneous platforms make it worthwhile for more developers to support SCI-MI-based models and for more users to make it part of their verification methodology.
The SCE-MI 2.1 standard
The ITC committee's goal is to reduce the effort necessary to get a system into an emulation or prototyping environment for verification. In order to do that the models at the boundaries -- transactors -- have to be as similar as possible to those that would have been used in a simulation environment. To do this, SCE-MI 2.1 incorporates a subset of the SystemVerilog DPI which is available in most simulators.
On top of this, a new transaction pipe interface has been defined, which adds support for variable length messaging and streaming data. Efficiency across the interface is paramount to getting the best possible utilization of the hardware, and these new capabilities add more control over when and how traffic moves around the system.
Version 2.1 speeds up electronic design verification since it allows a model developed for simulation to run in an emulation environment and vice versa. Version 2.1 has added support for a subset of the SystemVerilog Direct Programming Interface (DPI) and built a streaming, variable length messaging system on top of this, which reduces the number of synchronizations when compared to other available methodologies. Click here to download the standard.
"Accellera standards improve the electronic design experience for the semiconductor industry," remarked Shishpal Rawat, Accellera Chair. "We created this standard to alleviate one of the most critical bottlenecks in the electronic design cycle: verification. Given the reality of continually increasing design size and complexity, significant verification is enabled by SCE-MI as it allows simulation and emulation to be more interoperable."
"EDA suppliers are working to bring new SCE-MI 2.1 capabilities to their customers as quickly as possible, and our committee will continue to add features that address portability, performance and ease of use," said Brian Bailey, Interface Technical Committee (ITC) committee chair.
A previous version of the standard, SCE-MI 2.0, was approved by the Accellera Board in May 2007. The SCI-MI standard was first created and is being continually improved by Accellera's Interface Technical Committee (ITC).
The SCE-MI standard provides an easy way to connect and migrate transactor models between simulation, emulation and rapid prototyping environments. With it, design and verification teams can realize improved electronic design productivity. Model portability enhancements for transaction-level verification on heterogeneous platforms make it worthwhile for more developers to support SCI-MI-based models and for more users to make it part of their verification methodology.
The SCE-MI 2.1 standard
The ITC committee's goal is to reduce the effort necessary to get a system into an emulation or prototyping environment for verification. In order to do that the models at the boundaries -- transactors -- have to be as similar as possible to those that would have been used in a simulation environment. To do this, SCE-MI 2.1 incorporates a subset of the SystemVerilog DPI which is available in most simulators.
On top of this, a new transaction pipe interface has been defined, which adds support for variable length messaging and streaming data. Efficiency across the interface is paramount to getting the best possible utilization of the hardware, and these new capabilities add more control over when and how traffic moves around the system.
Friday, January 28, 2011
DelfMEMS and KFM Technology announce collaboration in RF MEMS packaging
LILLE & ORSAY, FRANCE: DelfMEMS and KFM Technology signed a common agreement to combine their expertise in RadioFrequency – RF - Micro-Electro-Mechanical Switches - MEMS - and Thin Film Packaging - TFP - technology. They are collaborating to enable DelfMEMS providing a low cost and very efficient RF MEMS technology platform and related products for mobile applications.
Since 2006, DelfMEMS and KFM Technology have respectively developed a patents portfolio concerning a innovative anchorless micro-mechanical devices dedicated to RF applications and a new approach to provide Thin Film Packaging/transferable high-Q passives.
DelfMEMS proposes a new integrated micro-mechanical building block that is based on a strong, totally new IP portfolio that solves past issues and substantially improves hot switching behavior, switching time (<1μs), and power consumption (12V actuation voltage, electrostatic). DelfMEMS develops a technology platform enabling its customers to increase bandwidth while minimizing cost, size, and consumption through technology integration or products.
KFM Technology provides collective encapsulation of components and MicroElectroMechanical Systems at the wafer-level (wafer-level packaging). Its R&D works aims to develop a technology of single-wafer packaging using the transfer of a polymer or metallic thin film microcap and its sealing around the device. Contrary to conventional MEMS assemblies techniques, this technology offers a total flexibility. It adapts to most constraints imposed by users and, by its collective and eventually re-usable approach, it significantly reduces fabrication costs.
The two companies enter a new step to combine both technologies. R&D teams will commonly adapt the packaging design according to the switch configuration, and will optimize the through packaging vias for RF performances. The innovative packaging combines the advantages of Wafer Level Packaging -such as low cost- with those of TFP such as small size, small thickness, higher frequency range -lower parasitic capacitance-, high integration and overmolding capability.
By using this technology, DelfMEMS does not need to change its MEMS process or to develop specific release/cleaning steps.
“Thin Film Packaging is a crucial point of our roadmap. We have investigated all MEMS packaging solutions. It has been a while to find such a technology fitting with all mobile market expectations : size & thickness, cost, integration, overmolding and performances.” explains Olivier Millet, CEO of DelfMEMS. “We have licenses from KFM Technology and are now collaborating to decrease the time-to-market. DelfMEMS had a disruptive RF MEMS technology, we are now going to have a doubly disruptive solution thanks to this partnership ”.
“Our Packaging Technology is extremely flexible, can provide almost any shape with any material on any substrate like Silicon, Glass...etc... This substrate could be also flexible like Kapton for example” says Martial Desgeorges, CEO of KFM Technology. "You can do much more interesting objects than Packages which is a particular function, our technology permits an easy and flexible 3D film tranfers to obtain low cost 3D objects" explains Fabrice Verjus, CTO of KFM Technology.
The last but not the least, combination of both technologies will enable DelfMEMS to provide packaged MEMS switches, fixed capacitors and high-Q inductors on the same chip, without modifying the fabrication process. A first step to propose high added value sub-systems with a MEMS switching technology platform.
Since 2006, DelfMEMS and KFM Technology have respectively developed a patents portfolio concerning a innovative anchorless micro-mechanical devices dedicated to RF applications and a new approach to provide Thin Film Packaging/transferable high-Q passives.
DelfMEMS proposes a new integrated micro-mechanical building block that is based on a strong, totally new IP portfolio that solves past issues and substantially improves hot switching behavior, switching time (<1μs), and power consumption (12V actuation voltage, electrostatic). DelfMEMS develops a technology platform enabling its customers to increase bandwidth while minimizing cost, size, and consumption through technology integration or products.
KFM Technology provides collective encapsulation of components and MicroElectroMechanical Systems at the wafer-level (wafer-level packaging). Its R&D works aims to develop a technology of single-wafer packaging using the transfer of a polymer or metallic thin film microcap and its sealing around the device. Contrary to conventional MEMS assemblies techniques, this technology offers a total flexibility. It adapts to most constraints imposed by users and, by its collective and eventually re-usable approach, it significantly reduces fabrication costs.
The two companies enter a new step to combine both technologies. R&D teams will commonly adapt the packaging design according to the switch configuration, and will optimize the through packaging vias for RF performances. The innovative packaging combines the advantages of Wafer Level Packaging -such as low cost- with those of TFP such as small size, small thickness, higher frequency range -lower parasitic capacitance-, high integration and overmolding capability.
By using this technology, DelfMEMS does not need to change its MEMS process or to develop specific release/cleaning steps.
“Thin Film Packaging is a crucial point of our roadmap. We have investigated all MEMS packaging solutions. It has been a while to find such a technology fitting with all mobile market expectations : size & thickness, cost, integration, overmolding and performances.” explains Olivier Millet, CEO of DelfMEMS. “We have licenses from KFM Technology and are now collaborating to decrease the time-to-market. DelfMEMS had a disruptive RF MEMS technology, we are now going to have a doubly disruptive solution thanks to this partnership ”.
“Our Packaging Technology is extremely flexible, can provide almost any shape with any material on any substrate like Silicon, Glass...etc... This substrate could be also flexible like Kapton for example” says Martial Desgeorges, CEO of KFM Technology. "You can do much more interesting objects than Packages which is a particular function, our technology permits an easy and flexible 3D film tranfers to obtain low cost 3D objects" explains Fabrice Verjus, CTO of KFM Technology.
The last but not the least, combination of both technologies will enable DelfMEMS to provide packaged MEMS switches, fixed capacitors and high-Q inductors on the same chip, without modifying the fabrication process. A first step to propose high added value sub-systems with a MEMS switching technology platform.
Defense semiconductor market to maintain growth
BOSTON, USA: While trying to save more than $150 billion over the next five years, the US Department of Defense will focus on technology which will translate into continued development on radar, EW (Electronic Warfare), communications and other advanced defense capabilities.
The Strategy Analytics Advanced Defense Systems (ADS) service report, “US DOD Budget Cuts will Place Emphasis on Advanced Electronics Capabilities,” predicts that this continued emphasis will translate into an upwards defense sector semiconductor market growth trajectory over 2010 - 2015 with a CAGR of over 6 percent.
These efficiency decisions are designed to save the Department of Defense more than $150 billion over the next five years primarily by:
* reducing overhead costs,
* improving business practices, and
* culling excess or troubled programs.
Most of the resulting savings will be used by the Army, Navy, Marine Corps and Air Force to invest in high priority programs that strengthen warfare capability.
“Despite defense budget growth dwindling to zero by 2015, there is recognition that the mistakes of the past should not be repeated by making drastic cuts to the overall defense budget,” stated Asif Anwar, ADS Service Director. “Progress made by China and Russia will require that the US continue its focus on technology.”
“Investment in high priority programs that strengthen fighting capability will translate into continued development on radar, EW, communications and other advanced defense issues,” noted Eric Higham, ADS Service Director North America. “Strategy Analytics believes that this will maintain demand for semiconductors with a particular emphasis on technologies such as GaAs (gallium arsenide), GaN (gallium nitride) and SiGe (Silicon Germanium).”
The Strategy Analytics Advanced Defense Systems (ADS) service report, “US DOD Budget Cuts will Place Emphasis on Advanced Electronics Capabilities,” predicts that this continued emphasis will translate into an upwards defense sector semiconductor market growth trajectory over 2010 - 2015 with a CAGR of over 6 percent.
These efficiency decisions are designed to save the Department of Defense more than $150 billion over the next five years primarily by:
* reducing overhead costs,
* improving business practices, and
* culling excess or troubled programs.
Most of the resulting savings will be used by the Army, Navy, Marine Corps and Air Force to invest in high priority programs that strengthen warfare capability.
“Despite defense budget growth dwindling to zero by 2015, there is recognition that the mistakes of the past should not be repeated by making drastic cuts to the overall defense budget,” stated Asif Anwar, ADS Service Director. “Progress made by China and Russia will require that the US continue its focus on technology.”
“Investment in high priority programs that strengthen fighting capability will translate into continued development on radar, EW, communications and other advanced defense issues,” noted Eric Higham, ADS Service Director North America. “Strategy Analytics believes that this will maintain demand for semiconductors with a particular emphasis on technologies such as GaAs (gallium arsenide), GaN (gallium nitride) and SiGe (Silicon Germanium).”
Synopsys to showcase DesignWare IP, FPGA design, FPGA-based prototyping and HSPICE solutions at DesignCon 2011
SANTA CLARA, USA: Synopsys Inc. will showcase its latest DesignWare® DDR PHY Compiler, Synplify FPGA design tools, HAPS FPGA-based prototyping platform, and HSPICE solutions at DesignCon 2011 in Santa Clara, California on February 1-2, 2011.
DesignCon is the definitive event for electronic design experts spanning chip, package, board, and system domains, addressing common issues in signal integrity, power management, interconnection and design verification.
DesignCon is the definitive event for electronic design experts spanning chip, package, board, and system domains, addressing common issues in signal integrity, power management, interconnection and design verification.
Workshop held on Karnataka semicon policy
BANGALORE, INDIA: The government of Karnataka has launched the “Karnataka Semiconductor Policy 2010” on 25-02-2010 to give an impetus to the growth of Semiconductor Industries in the State. The Policy Document is available in the Departmental website www.bangaloreitbt.in.
In order to enable the Semiconductor Companies to avail the benefits enumerated in the Policy, and to create awareness among the industrialists a half-dayseminar has been organized by the Department of IT, BT and S&T, in coordination with ISA and MAIT, today in the Ball Room of The LaLiT Ashok Hotel, Bangalore.
Focus of the Policy is as follows:
a)Retain its edge in design by attracting fresh investments and expansion by existing companies within the state.
b)Attract manufacturing related investments by focusing on 3 key activities.
I. Promote Karnataka as a semiconductor design hub.
II. Attract investments in high-tech semiconductor manufacturing.
III. Promote generation and use of green energy – specifically, solar energy.
IV. Focus on manpower development.
Salient features of semicon policy
a) As a policy support to encourage innovation and R&D in chip design, product development, telecom, etc., the government will set up a fund known as ‘KARNATAKA FUND FOR SEMICONDUCTOR EXCELLENCE’ of Rs.10 crores. This fund will be available to the private companies covering up to 50 percent of their R&D expenses, subject to a limit of Rs 10 lakhs per unit.
b) Provide additional amount of Rs. 25 crores, toward 26 percent contribution to the KITVEN IT Fund for raising funds from the market to assist start up semi-conductor units engaged in design and embedded software.
c) Provide incentives set up in the state by lowering the threshold investment for ATMPs/ecosystem units with investment above Rs. 400 crores and up to Rs. 1,000 crores.
d) Provide assistance of 50 percent of the total cost toward purchase of proposed equipment, for augmenting the Orchid Tech Space in STPI to a Characterization Lab.
e) Provide financial assistance to firms for filing IP in accordance with the incentives provided in the Industrial Policy 2009-2014.
f) To encourage setting up of semiconductor units in Tier-2 cities including Mysore, Mangalore, Hubli an incentive of Investment Promotion Subsidy would be provided in accordance with the Karnataka Industrial Policy 2009-14.
g) Government to set up a focused school under IIIT at a cost of Rs. 10 crores and strengthen the Research Labs in the institute at a cost of Rs. 5 crores, with a contribution of 25 percent from the industry.
h) ATMP units will be encouraged with special incentives in the proposed ITIR near BIAL, Bangalore (Special incentives for the ITIR to be announced separately).
The following fiscal incentives would be provided to semiconductor units as per the Karnataka Industrial Policy 2009-2014:
1. Investment Promotion Subsidy.
2. Exemption from Stamp Duty to MSME, Large and Mega Projects.
3. Concessional Registration Charges to MSME, Large and Mega Projects.
4. Waiver of Conversion Fine to MSME, Large and Mega Projects.
5. Exemption from Entry Tax to MSME, Large and Mega Projects.
6. Incentives for Exported Oriented Enterprises to MSME, Large and Mega Projects.
7. Subsidy for setting up ETPs to MSME, Large and Mega Projects.
8. Interest Free Loan on VAT to Large and MEGa Projects.
9. Anchor Unit Subsidy to first two Manufacturing Enterprises with minimum employment of 100 members and minimum investment of Rs. 50 crore.
10. Special incentives for Enterprises coming up in low HDI districts only for large and mega Projects.
11. Interest Subsidy to Micro manufacturing enterprises.
12. Exemption from Electricity Duty to Micro and Small manufacturing enterprises.
13. Technology upgradation, quality certification and patent registration micro and small manufacturing enterprises.
14. Water harvesting/conservation measures to small and medium manufacturing enterprises in all zones.
15. Energy conservation for small and medium manufacturing enterprises in all zones.
16. Additional incentives to the enterprises following Reservation Policy of the state.
17. Refund of cost incurred for preparation Project Report for micro and small manufacturing enterprises.
Inaugurating the session, Aravind Jannu IAS, director, Directorate of IT & BT & MD, KBITS said:“Indian semiconductor design industry is expected to reach $7.5 billion in 2011. Karnataka is currently home to over 80 design companies and contributes significantly to the overall revenue. The Karnataka Semiconductor Policy 2010 is aimed at further strengthening Karnataka’s leadership in the chip design and embedded software. We now want to extend this strength into high tech manufacturing and the government is working closely with ISA and other industry bodies in creating industry friendly policies that will attract investors.”
Dr. Pradip K. Dutta, vice chairman, ISA and corporate VP, Synopsys Inc and MD, Synopsys (India) Pvt Ltd said: “By 2020 electronics consumption in India will reach $400 billion, today it stands at $45 billion and over 80 percent of it is imported. There is an urgent need to focus on domestic Electronic System Design and Manufacturing (ESDM) industry and work towards enabling this ecosystem. If not, import bill for electronics will soon exceed that of oil.”
In order to enable the Semiconductor Companies to avail the benefits enumerated in the Policy, and to create awareness among the industrialists a half-dayseminar has been organized by the Department of IT, BT and S&T, in coordination with ISA and MAIT, today in the Ball Room of The LaLiT Ashok Hotel, Bangalore.
Focus of the Policy is as follows:
a)Retain its edge in design by attracting fresh investments and expansion by existing companies within the state.
b)Attract manufacturing related investments by focusing on 3 key activities.
I. Promote Karnataka as a semiconductor design hub.
II. Attract investments in high-tech semiconductor manufacturing.
III. Promote generation and use of green energy – specifically, solar energy.
IV. Focus on manpower development.
Salient features of semicon policy
a) As a policy support to encourage innovation and R&D in chip design, product development, telecom, etc., the government will set up a fund known as ‘KARNATAKA FUND FOR SEMICONDUCTOR EXCELLENCE’ of Rs.10 crores. This fund will be available to the private companies covering up to 50 percent of their R&D expenses, subject to a limit of Rs 10 lakhs per unit.
b) Provide additional amount of Rs. 25 crores, toward 26 percent contribution to the KITVEN IT Fund for raising funds from the market to assist start up semi-conductor units engaged in design and embedded software.
c) Provide incentives set up in the state by lowering the threshold investment for ATMPs/ecosystem units with investment above Rs. 400 crores and up to Rs. 1,000 crores.
d) Provide assistance of 50 percent of the total cost toward purchase of proposed equipment, for augmenting the Orchid Tech Space in STPI to a Characterization Lab.
e) Provide financial assistance to firms for filing IP in accordance with the incentives provided in the Industrial Policy 2009-2014.
f) To encourage setting up of semiconductor units in Tier-2 cities including Mysore, Mangalore, Hubli an incentive of Investment Promotion Subsidy would be provided in accordance with the Karnataka Industrial Policy 2009-14.
g) Government to set up a focused school under IIIT at a cost of Rs. 10 crores and strengthen the Research Labs in the institute at a cost of Rs. 5 crores, with a contribution of 25 percent from the industry.
h) ATMP units will be encouraged with special incentives in the proposed ITIR near BIAL, Bangalore (Special incentives for the ITIR to be announced separately).
The following fiscal incentives would be provided to semiconductor units as per the Karnataka Industrial Policy 2009-2014:
1. Investment Promotion Subsidy.
2. Exemption from Stamp Duty to MSME, Large and Mega Projects.
3. Concessional Registration Charges to MSME, Large and Mega Projects.
4. Waiver of Conversion Fine to MSME, Large and Mega Projects.
5. Exemption from Entry Tax to MSME, Large and Mega Projects.
6. Incentives for Exported Oriented Enterprises to MSME, Large and Mega Projects.
7. Subsidy for setting up ETPs to MSME, Large and Mega Projects.
8. Interest Free Loan on VAT to Large and MEGa Projects.
9. Anchor Unit Subsidy to first two Manufacturing Enterprises with minimum employment of 100 members and minimum investment of Rs. 50 crore.
10. Special incentives for Enterprises coming up in low HDI districts only for large and mega Projects.
11. Interest Subsidy to Micro manufacturing enterprises.
12. Exemption from Electricity Duty to Micro and Small manufacturing enterprises.
13. Technology upgradation, quality certification and patent registration micro and small manufacturing enterprises.
14. Water harvesting/conservation measures to small and medium manufacturing enterprises in all zones.
15. Energy conservation for small and medium manufacturing enterprises in all zones.
16. Additional incentives to the enterprises following Reservation Policy of the state.
17. Refund of cost incurred for preparation Project Report for micro and small manufacturing enterprises.
Inaugurating the session, Aravind Jannu IAS, director, Directorate of IT & BT & MD, KBITS said:“Indian semiconductor design industry is expected to reach $7.5 billion in 2011. Karnataka is currently home to over 80 design companies and contributes significantly to the overall revenue. The Karnataka Semiconductor Policy 2010 is aimed at further strengthening Karnataka’s leadership in the chip design and embedded software. We now want to extend this strength into high tech manufacturing and the government is working closely with ISA and other industry bodies in creating industry friendly policies that will attract investors.”
Dr. Pradip K. Dutta, vice chairman, ISA and corporate VP, Synopsys Inc and MD, Synopsys (India) Pvt Ltd said: “By 2020 electronics consumption in India will reach $400 billion, today it stands at $45 billion and over 80 percent of it is imported. There is an urgent need to focus on domestic Electronic System Design and Manufacturing (ESDM) industry and work towards enabling this ecosystem. If not, import bill for electronics will soon exceed that of oil.”
Cortus presents range of embedded processors at DesignCon2011 with Avant
FRANCE: Cortus will present its range of processors for embedded systems at this year’s DesignCon2011 with their partner Avant Technology. The Cortus family of processors for embedded systems offer a complete range of solutions for embedded systems designers.
Cortus has processors for designers who need a highly cost effective processor. They also have solutions for designers who need high performance multi-core systems yet have only tiny power and silicon budgets.
Avant Technology represents the entire range of Cortus’ products. For embedded systems designers, requiring a simple controller, complete solutions requiring very low power and a tiny silicon footprint are available. A full IDE with complete tool support is available as well as standard peripherals such as bridges, I/O, USB2.0, Ethernet, sophisticated interrupt controllers. Small and compact real time operating systems such as OpenRTOS are also supported.
Avant Technology can also supply Cortus’ high performance multi-core solutions which include full tool support, compilers, debuggers, IDE and simulators; advanced functions such as memory management units (MMUs) and configurable caches (both instruction and coherent snoopy data caches). Support is also offered for operating systems, such as Linux.
Cortus’ products are currently in production in a range of products, from mobile telephones to SIM cards and other challenging environments such as video cameras, smart cards for pay TV, ultra low power RF. Our customers appreciate not only our very low power and tiny silicon footprint but also the flexibility of our cores. Certain customers have customised the processors to their specific application space, for example with cryptographic coprocessors that significantly increase the performance and efficiency of their solution.
Cortus has processors for designers who need a highly cost effective processor. They also have solutions for designers who need high performance multi-core systems yet have only tiny power and silicon budgets.
Avant Technology represents the entire range of Cortus’ products. For embedded systems designers, requiring a simple controller, complete solutions requiring very low power and a tiny silicon footprint are available. A full IDE with complete tool support is available as well as standard peripherals such as bridges, I/O, USB2.0, Ethernet, sophisticated interrupt controllers. Small and compact real time operating systems such as OpenRTOS are also supported.
Avant Technology can also supply Cortus’ high performance multi-core solutions which include full tool support, compilers, debuggers, IDE and simulators; advanced functions such as memory management units (MMUs) and configurable caches (both instruction and coherent snoopy data caches). Support is also offered for operating systems, such as Linux.
Cortus’ products are currently in production in a range of products, from mobile telephones to SIM cards and other challenging environments such as video cameras, smart cards for pay TV, ultra low power RF. Our customers appreciate not only our very low power and tiny silicon footprint but also the flexibility of our cores. Certain customers have customised the processors to their specific application space, for example with cryptographic coprocessors that significantly increase the performance and efficiency of their solution.
TI delivers highly efficient Class-G amp for cost-sensitive media players and mobile handsets
BANGALORE, INDIA: Texas Instruments Inc. (TI) has introduced a low-power Class-G headphone amplifier with an integrated digital-to-analog converter (DAC) and power rails for mobile handsets and media players.
The TLV320DAC3202 is the only standalone headset driver with digital input I2S and an integrated clocking system that delivers 100-dB SNR at 6.5-mW power dissipation. The new amplifier allows designers to maximize audio playback quality while extending battery life in moderately priced music phones and other portable consumer electronics.
Key features and benefits of the TLV320DAC3202
• Features industry’s lowest power consumption at 100-dB signal-to-noise ratio (SNR); 3 to 4 dB above the industry standard, with 6.5-mW power dissipation.
• Highly efficient power management technology with the TPS62044 facilitates seamless operation between battery and switched mode input voltage supply for efficient playback, even in systems with minimal input voltage current budget.
• Excellent power supply rejection ratio (PSRR) enables direct power from efficient asynchronous switched mode input voltage supply at 100 dB per channel SNR, eliminating the need for linear regulators for supplies.
• Innovative circuit techniques cut click-pop noise in half compared to leading competitors.
• Aggressive 2-mm x 2.5-mm footprint achieved through TI’s 130-nm analog process technology and circuit techniques minimizes the overall bill of materials and solution size/cost.
The TLV320DAC3202 is the only standalone headset driver with digital input I2S and an integrated clocking system that delivers 100-dB SNR at 6.5-mW power dissipation. The new amplifier allows designers to maximize audio playback quality while extending battery life in moderately priced music phones and other portable consumer electronics.
Key features and benefits of the TLV320DAC3202
• Features industry’s lowest power consumption at 100-dB signal-to-noise ratio (SNR); 3 to 4 dB above the industry standard, with 6.5-mW power dissipation.
• Highly efficient power management technology with the TPS62044 facilitates seamless operation between battery and switched mode input voltage supply for efficient playback, even in systems with minimal input voltage current budget.
• Excellent power supply rejection ratio (PSRR) enables direct power from efficient asynchronous switched mode input voltage supply at 100 dB per channel SNR, eliminating the need for linear regulators for supplies.
• Innovative circuit techniques cut click-pop noise in half compared to leading competitors.
• Aggressive 2-mm x 2.5-mm footprint achieved through TI’s 130-nm analog process technology and circuit techniques minimizes the overall bill of materials and solution size/cost.
Freescale announces Q4 and full-year 2010 results
AUSTIN, USA: Freescale Semiconductor Holdings I. Ltd has announced financial results for the fourth quarter and fiscal year ended December 31, 2010.
Highlights for the fourth quarter and calendar year include:
* Net sales of $1.18 billion for the fourth quarter;
* Net sales of $4.46 billion for fiscal year 2010;
* Trailing twelve month Adjusted EBITDA of $1.15 billion;
* Cash and cash equivalents of $1.04 billion at December 31, 2010.
“Our fourth quarter results cap off a solid performance in 2010 with revenue growth, margin expansion and record design wins,” said Rich Beyer, chairman and CEO. “The momentum we saw throughout the year positions us for continued improvement in 2011.”
Operating results
Net sales for the fourth quarter of 2010 were $1.18 billion, compared to $1.15 billion in the third quarter of 2010 and $951 million in the fourth quarter last year. Net sales for calendar year 2010 were $4.46 billion, compared to $3.51 billion in calendar year 2009.
Income from operations for the three months ended December 31, 2010 was $17 million, compared to $1 million in the third quarter of 2010 and a loss of $261 million in the fourth quarter of 2009. Income from operations for calendar year 2010 was a loss of $61 million compared to a loss of $1.22 billion in calendar year 2009.
Adjusted operating earnings (defined in Note 1 to the Notes to the Consolidated Financial Information attached to this press release) for the three months ended December 31, 2010, were $177 million compared to earnings of $158 million in the third quarter of 2010 and $59 million in the fourth quarter of 2009. Adjusted operating earnings for calendar year 2010 were $566 million compared to a loss of $144 million in calendar year 2009.
Earnings before Interest, Taxes, Depreciation and Amortization (EBITDA) (defined in Note 1 to the Notes to the Consolidated Financial Information attached to this press release) was $280 million for the fourth quarter of 2010, compared to $253 million in the third quarter of 2010 and $168 million in the fourth quarter of 2009. EBITDA for calendar year 2010 was $957 million compared to $304 million in calendar year 2009.
Descriptions of adjusted gross margin, EBITDA, Adjusted EBITDA and adjusted operating earnings (loss) and the reconciliations to our GAAP results are included in the tables and notes attached to this press release.
Product revenues
The company’s net sales figures for the fourth quarter and full year 2010 are as follows:
* Microcontroller net sales were $415 million in the fourth quarter of 2010, compared to $418 million in the third quarter of 2010 and $333 million in the fourth quarter of 2009. Microcontroller net sales for calendar 2010 were $1.59 billion compared to $1.11 billion in calendar year 2009.
* RF, Analog and Sensor net sales were $285 million in the fourth quarter of 2010, compared to $272 million in the third quarter of 2010 and $221 million in the fourth quarter of 2009. RF, Analog and Sensor net sales for calendar year 2010 were $1.06 billion compared to $814 million in calendar year 2009.
* Networking and Multimedia net sales were $338 million in the fourth quarter of 2010, compared to $338 million in the third quarter of 2010 and $251 million in the fourth quarter of 2009. Networking and Multimedia net sales for calendar year 2010 were $1.23 billion compared to $929 million in calendar year 2009.
* Cellular net sales were $111 million in the fourth quarter of 2010, compared to $90 million in the third quarter of 2010 and $116 million in the fourth quarter of 2009. * Cellular net sales for calendar year 2010 were $455 million compared to $471 million in calendar year 2009.
* Other net sales were $33 million in the fourth quarter of 2010 compared to $30 million in the third quarter of 2010 and $30 million in the fourth quarter of 2009. Other net sales for calendar year 2010 were $120 million, compared to $180 million in calendar year 2009.
Highlights for the fourth quarter and calendar year include:
* Net sales of $1.18 billion for the fourth quarter;
* Net sales of $4.46 billion for fiscal year 2010;
* Trailing twelve month Adjusted EBITDA of $1.15 billion;
* Cash and cash equivalents of $1.04 billion at December 31, 2010.
“Our fourth quarter results cap off a solid performance in 2010 with revenue growth, margin expansion and record design wins,” said Rich Beyer, chairman and CEO. “The momentum we saw throughout the year positions us for continued improvement in 2011.”
Operating results
Net sales for the fourth quarter of 2010 were $1.18 billion, compared to $1.15 billion in the third quarter of 2010 and $951 million in the fourth quarter last year. Net sales for calendar year 2010 were $4.46 billion, compared to $3.51 billion in calendar year 2009.
Income from operations for the three months ended December 31, 2010 was $17 million, compared to $1 million in the third quarter of 2010 and a loss of $261 million in the fourth quarter of 2009. Income from operations for calendar year 2010 was a loss of $61 million compared to a loss of $1.22 billion in calendar year 2009.
Adjusted operating earnings (defined in Note 1 to the Notes to the Consolidated Financial Information attached to this press release) for the three months ended December 31, 2010, were $177 million compared to earnings of $158 million in the third quarter of 2010 and $59 million in the fourth quarter of 2009. Adjusted operating earnings for calendar year 2010 were $566 million compared to a loss of $144 million in calendar year 2009.
Earnings before Interest, Taxes, Depreciation and Amortization (EBITDA) (defined in Note 1 to the Notes to the Consolidated Financial Information attached to this press release) was $280 million for the fourth quarter of 2010, compared to $253 million in the third quarter of 2010 and $168 million in the fourth quarter of 2009. EBITDA for calendar year 2010 was $957 million compared to $304 million in calendar year 2009.
Descriptions of adjusted gross margin, EBITDA, Adjusted EBITDA and adjusted operating earnings (loss) and the reconciliations to our GAAP results are included in the tables and notes attached to this press release.
Product revenues
The company’s net sales figures for the fourth quarter and full year 2010 are as follows:
* Microcontroller net sales were $415 million in the fourth quarter of 2010, compared to $418 million in the third quarter of 2010 and $333 million in the fourth quarter of 2009. Microcontroller net sales for calendar 2010 were $1.59 billion compared to $1.11 billion in calendar year 2009.
* RF, Analog and Sensor net sales were $285 million in the fourth quarter of 2010, compared to $272 million in the third quarter of 2010 and $221 million in the fourth quarter of 2009. RF, Analog and Sensor net sales for calendar year 2010 were $1.06 billion compared to $814 million in calendar year 2009.
* Networking and Multimedia net sales were $338 million in the fourth quarter of 2010, compared to $338 million in the third quarter of 2010 and $251 million in the fourth quarter of 2009. Networking and Multimedia net sales for calendar year 2010 were $1.23 billion compared to $929 million in calendar year 2009.
* Cellular net sales were $111 million in the fourth quarter of 2010, compared to $90 million in the third quarter of 2010 and $116 million in the fourth quarter of 2009. * Cellular net sales for calendar year 2010 were $455 million compared to $471 million in calendar year 2009.
* Other net sales were $33 million in the fourth quarter of 2010 compared to $30 million in the third quarter of 2010 and $30 million in the fourth quarter of 2009. Other net sales for calendar year 2010 were $120 million, compared to $180 million in calendar year 2009.
NAND flash contract prices update
TAIWAN: According to DRAMeXchange, a research department of Trendforce, 2H January, mainstream NAND Flash price remains flat while 128Gb price is up 8.7 percent compared to price in 1H January.
We find the mixed dynamics between system products, retail memory card and UFD affecting the price. First, most memory card makers have restocked inventory before mid-January and are more reluctant to increase because retail memory card and UFD sales are lacking significant momentum. Second, system products such as Smartphone and tablet PC are gradually showing strong demand for embedded NAND Flash and the demand for new model will help to sustain the price.
Due to the mix of these factors mentioned above, the mainstream NAND Flash price remains unchanged.
DRAMeXchange expects the mainstream NAND Flash price will decrease after the Chinese New Year given the coming slow season for consumer electronics. However, the situation could vary if system products such as tablet and Smartphone outperformed our expectation.
We find the mixed dynamics between system products, retail memory card and UFD affecting the price. First, most memory card makers have restocked inventory before mid-January and are more reluctant to increase because retail memory card and UFD sales are lacking significant momentum. Second, system products such as Smartphone and tablet PC are gradually showing strong demand for embedded NAND Flash and the demand for new model will help to sustain the price.
Due to the mix of these factors mentioned above, the mainstream NAND Flash price remains unchanged.
DRAMeXchange expects the mainstream NAND Flash price will decrease after the Chinese New Year given the coming slow season for consumer electronics. However, the situation could vary if system products such as tablet and Smartphone outperformed our expectation.
Intel simplifies the data center
SANTA CLARA, USA: Intel Corp. took a further step today to simplify the data center by introducing a free new technology that enables all data center traffic to run over a single cable using the Intel 10 Gigabit Ethernet (10 GbE) Server Adapter X520 family.
Unified networking allows IT departments to create flexible superhighways in virtualized data centers by consolidating multiple data and storage networks onto a single 10GbE network. The consolidation of cabling equipment can help reduce global IT spending by $3 billion a year, and the 400 million feet of global data center cabling saved is enough to wrap around the Earth three times.
A simple and high-speed unified data center network is a cornerstone of Intel’s Cloud 2015 vision and Open Data Center initiative, which were announced in October. Unified networking on 10GbE creates a simpler data center infrastructure that is easier to manage, yet can accommodate the heavy network traffic of the cloud.
“What’s frustrating for IT managers is that most of the data center dollars are spent on infrastructure costs, not on innovation,” said Kirk Skaugen, vice president and general manager, Data Center Group, Intel. “Expanding Intel Ethernet to include Open FCoE will help simplify the network and drive more of the IT budget toward innovation. We think IT departments can lower infrastructure costs by 29 percent, reduce power by almost 50 percent and cut cable costs by 80 percent by moving to a unified network.”
Intel’s Open FCoE integrates capabilities into the operating system to deliver full unified networking without the need for additional expensive, proprietary hardware. IT departments can use common management tools for server network and storage connectivity while integrating seamlessly with existing Fibre Channel environments.
“A unified fabric supports both compute and storage resources over a high-bandwidth transport to deliver greater data center efficiency, simplify management and can accelerate the deployment of virtualization and cloud-based services,” said Soni Jiandani, vice president of marketing, Server Access and Virtualization Technology Group, Cisco.
“The Cisco Nexus 10 Gigabit Ethernet switches and the Cisco Unified Computing System servers both support Intel’s Open FCoE 10 Gigabit Ethernet adapters to provide our customers with greater choice for cost-effective, scalable unified fabric access.”
Intel has worked closely with key industry leaders to certify and ensure a strong ecosystem of compatible solutions. Companies supporting the Open FCoE solution include Cisco, Dell, EMC, NetApp, Oracle and Red Hat.
The Intel Open FCoE software stack is available as a free upgrade on existing X520 family products.
Unified networking allows IT departments to create flexible superhighways in virtualized data centers by consolidating multiple data and storage networks onto a single 10GbE network. The consolidation of cabling equipment can help reduce global IT spending by $3 billion a year, and the 400 million feet of global data center cabling saved is enough to wrap around the Earth three times.
A simple and high-speed unified data center network is a cornerstone of Intel’s Cloud 2015 vision and Open Data Center initiative, which were announced in October. Unified networking on 10GbE creates a simpler data center infrastructure that is easier to manage, yet can accommodate the heavy network traffic of the cloud.
“What’s frustrating for IT managers is that most of the data center dollars are spent on infrastructure costs, not on innovation,” said Kirk Skaugen, vice president and general manager, Data Center Group, Intel. “Expanding Intel Ethernet to include Open FCoE will help simplify the network and drive more of the IT budget toward innovation. We think IT departments can lower infrastructure costs by 29 percent, reduce power by almost 50 percent and cut cable costs by 80 percent by moving to a unified network.”
Intel’s Open FCoE integrates capabilities into the operating system to deliver full unified networking without the need for additional expensive, proprietary hardware. IT departments can use common management tools for server network and storage connectivity while integrating seamlessly with existing Fibre Channel environments.
“A unified fabric supports both compute and storage resources over a high-bandwidth transport to deliver greater data center efficiency, simplify management and can accelerate the deployment of virtualization and cloud-based services,” said Soni Jiandani, vice president of marketing, Server Access and Virtualization Technology Group, Cisco.
“The Cisco Nexus 10 Gigabit Ethernet switches and the Cisco Unified Computing System servers both support Intel’s Open FCoE 10 Gigabit Ethernet adapters to provide our customers with greater choice for cost-effective, scalable unified fabric access.”
Intel has worked closely with key industry leaders to certify and ensure a strong ecosystem of compatible solutions. Companies supporting the Open FCoE solution include Cisco, Dell, EMC, NetApp, Oracle and Red Hat.
The Intel Open FCoE software stack is available as a free upgrade on existing X520 family products.
Tablet DRAM demand surges by factor of nine in 2011
EL SEGUNDO, USA: Bucking weak conditions for the overall dynamic random access memory (DRAM) market in 2011, DRAM shipments for tablets are expected to explode by a factor of more than nine this year, according to new IHS iSuppli research.
DRAM shipments this year for tablet devices are projected to reach 353.3 million gigabits (Gb), up a staggering 834.7 percent from a mere 37.8 million in 2010. Shipments of tablet DRAM—the main memory component in these devices—will continue to rise during the years to come, surging to 1.0 billion Gb in 2012, to 2.2 billion Gb in 2013 and to 3.5 billion Gb in 2014, as shown in the figure.
Source: IHS iSuppli.
“The DRAM industry is receiving a major boost from tablets, the undisputed stars of this year’s Consumer Electronics Show (CES) in Las Vegas,” said Mike Howard, principal analyst for DRAM & memory at IHS. “At the show, new tablets such as the Xoom from Motorola Inc. and the BlackBerry Playbook from Research in Motion joined recently released rival products made by Samsung Electronics and Dell Inc.—devices all intended to dent the overwhelming lead for Apple Inc.’s iPad.”
Worldwide tablet shipments this year are forecast to hit 57.6 million, up from 17.1 million in 2010. Shipments will continue to climb during the next few years.
The strength of memory shipments for tablets contrasts with the weak performance of the overall DRAM market in 2011, where continually retreating average selling prices are expected to spur an 11.8 percent decline in revenue this year.
Tablet challenges for DRAM suppliers
Despite the heady opportunities presented by tablets for the memory industry, some challenges could be in store for DRAM suppliers.
A first challenge concerns the amount of DRAM used by tablets. Many compelling tablet models shown at this year’s CES contained 1 gigabyte (GB) of mobile DRAM—far less than the average 3.2GB of memory used at the end of the fourth quarter in 2010 for PCs—the single largest segment that uses DRAM.
Furthermore, while the majority of tablets at the show used the more expensive mobile DRAM, there also were tablets running ARM microprocessors utilizing commodity DRAM—potentially a damaging trend for DRAM companies in light of commodity DRAM’s lower margins.
A second test centers on worries that tablets will eat into some PC sales, especially netbooks, which boast similar computing power to tablets. Although netbooks offer the advantage of lower prices, the light weight and long battery life of tablets increase their attractiveness for many consumers. As a result, sales of netbooks stand in serious danger of being cannibalized by tablets, Howard noted.
Source: IHS iSuppli.
DRAM shipments this year for tablet devices are projected to reach 353.3 million gigabits (Gb), up a staggering 834.7 percent from a mere 37.8 million in 2010. Shipments of tablet DRAM—the main memory component in these devices—will continue to rise during the years to come, surging to 1.0 billion Gb in 2012, to 2.2 billion Gb in 2013 and to 3.5 billion Gb in 2014, as shown in the figure.
Source: IHS iSuppli.“The DRAM industry is receiving a major boost from tablets, the undisputed stars of this year’s Consumer Electronics Show (CES) in Las Vegas,” said Mike Howard, principal analyst for DRAM & memory at IHS. “At the show, new tablets such as the Xoom from Motorola Inc. and the BlackBerry Playbook from Research in Motion joined recently released rival products made by Samsung Electronics and Dell Inc.—devices all intended to dent the overwhelming lead for Apple Inc.’s iPad.”
Worldwide tablet shipments this year are forecast to hit 57.6 million, up from 17.1 million in 2010. Shipments will continue to climb during the next few years.
The strength of memory shipments for tablets contrasts with the weak performance of the overall DRAM market in 2011, where continually retreating average selling prices are expected to spur an 11.8 percent decline in revenue this year.
Tablet challenges for DRAM suppliers
Despite the heady opportunities presented by tablets for the memory industry, some challenges could be in store for DRAM suppliers.
A first challenge concerns the amount of DRAM used by tablets. Many compelling tablet models shown at this year’s CES contained 1 gigabyte (GB) of mobile DRAM—far less than the average 3.2GB of memory used at the end of the fourth quarter in 2010 for PCs—the single largest segment that uses DRAM.
Furthermore, while the majority of tablets at the show used the more expensive mobile DRAM, there also were tablets running ARM microprocessors utilizing commodity DRAM—potentially a damaging trend for DRAM companies in light of commodity DRAM’s lower margins.
A second test centers on worries that tablets will eat into some PC sales, especially netbooks, which boast similar computing power to tablets. Although netbooks offer the advantage of lower prices, the light weight and long battery life of tablets increase their attractiveness for many consumers. As a result, sales of netbooks stand in serious danger of being cannibalized by tablets, Howard noted.
Source: IHS iSuppli.
National Semiconductor's 10 Gbps repeaters double signal conditioning performance at half the power
SANTA CLARA, USA: Extending its leadership in high-performance analog technology, National Semiconductor Corp. has announced three multi-channel PowerWise 10 Gbps repeaters that provide the industry's highest equalization gain (36 dB), consume half the power (55 mW/channel) and deliver twice the reach (20 meters over 24-AWG cable) of current industry solutions.
Powered by National's third-generation SiGe BiCMOS process, National's 10 Gbps repeater family extends interconnect reach and enables higher data bandwidth up to 10.3125 Gbps by performing both receive equalization and transmit de-emphasis to compensate for channel loss in data center and high-performance communication systems.
Target applications include high-speed active cable assemblies and FR-4 backplanes using serial protocols such as 10 GbE, Fibre Channel, XAUI, CPRI and Infiniband. The repeaters also support SAS/SATA out of band (OOB) signaling for storage applications.
The explosion of multimedia content on the Internet, cloud computing, and the advent of multi-core virtualized servers are pushing interface bandwidth requirements in modern data center systems. However, interconnect length remains the same, posing power and signal integrity issues. National's signal conditioners embedded inside the active copper cable assemblies and backplane boards ensure signal integrity, reduce system power consumption and lower interconnect cost compared to optical alternatives.
National's 10 Gbps repeaters enable these active copper solutions to consume 4x lower power and 2x longer reach than competitive cabling solutions through the use of a new SiGe BiCMOS process, which produces high bandwidth and low noise transistors that enable low jitter and ultra-low power. The quad DS100BR410 is well-suited for high density connectors such as QSFP and CXP, while the DS100BR111 is designed for single lane SFP+ connectors.
Powered by National's third-generation SiGe BiCMOS process, National's 10 Gbps repeater family extends interconnect reach and enables higher data bandwidth up to 10.3125 Gbps by performing both receive equalization and transmit de-emphasis to compensate for channel loss in data center and high-performance communication systems.
Target applications include high-speed active cable assemblies and FR-4 backplanes using serial protocols such as 10 GbE, Fibre Channel, XAUI, CPRI and Infiniband. The repeaters also support SAS/SATA out of band (OOB) signaling for storage applications.
The explosion of multimedia content on the Internet, cloud computing, and the advent of multi-core virtualized servers are pushing interface bandwidth requirements in modern data center systems. However, interconnect length remains the same, posing power and signal integrity issues. National's signal conditioners embedded inside the active copper cable assemblies and backplane boards ensure signal integrity, reduce system power consumption and lower interconnect cost compared to optical alternatives.
National's 10 Gbps repeaters enable these active copper solutions to consume 4x lower power and 2x longer reach than competitive cabling solutions through the use of a new SiGe BiCMOS process, which produces high bandwidth and low noise transistors that enable low jitter and ultra-low power. The quad DS100BR410 is well-suited for high density connectors such as QSFP and CXP, while the DS100BR111 is designed for single lane SFP+ connectors.
Microsemi announces high-level synthesis support from Synopsys
IRVINE, USA: Microsemi Corp., a leading provider of semiconductor technology aimed at building a smart, secure, connected world, announced that Synopsys' Synphony Model Compiler, a design tool suite for hardware DSP algorithm design, now provides support for Microsemi FPGAs.
Synphony Model Compiler enables easier and more reliable FPGA execution of algorithms by offering a more automated implementation and verification flow for engineers using MATLAB/Simulink.
The software tool achieves significantly higher productivity than alternative MATLAB/Simulink flows and gives the designer a mechanism to quickly evaluate high-level area and performance trade-offs. Synphony Model Compiler supports many of Microsemi's FPGAs, including the RTAX-DSP, RTAX-S/SL, Axcelerator, as well as the ProASIC3, IGLOO, and Fusion devices.
Synphony Model Compiler delivers performance and productivity benefits for designers who are implementing DSP circuits into FPGAs. For algorithm designers, the software offers advanced high-level synthesis in their chosen design environment and automates a smooth transition into the Synopsys FPGA logic implementation flow.
For the hardware engineer, the software eliminates costly iterations normally required to create optimum RTL from the DSP algorithm design intent, because it generates the necessary RTL code and offers built-in optimizations that account for device-specific features.
Included in the software:
* A synthesizable IP model library for the MATLAB/Simulink environment for wireless, multimedia and signal processing applications.
* High-level synthesis to automatically produce a bit-exact, optimized HDL implementation.
* An automated flow to capture test vectors from the high-level model.
* Automatic HDL test bench generation to verify bit accuracy.
* Creation of C-models representing the final RTL for use in hardware and software verification flow (optional package required).
* Integration with Synplify Pro logic synthesis for efficient FPGA implementation.
"Microsemi devices offer significant value in integration, performance and flexibility for designers of electronic systems. However, design teams need faster and more productive ways to get the most out of these devices," said Chris Eddington, product marketing director at Synopsys.
"Synphony Model Compiler enables engineers to explore and implement their ideas much more quickly and from higher levels of abstraction than traditional HDL flows. By collaborating with Microsemi's SoC Products Group on high-level design flows like Synphony Model Compiler, we can deliver much greater design and verification productivity to our mutual customers."
"The RTAX-DSP family of DSP-enabled space flight FPGAs combine the advantages of efficient integration of DSP algorithms with high levels of tolerance to the damaging effects of radiation encountered in space," states Ken O'Neill, director of high reliability product marketing at Microsemi's SoC Products Group. "Synopsys' Synphony Model Compiler is an important tool in our Libero IDE design suite to efficiently manage and optimize DSP designs."
Synphony Model Compiler AE licenses are available to Actel customers at no cost. For more information and to receive your free license, visit the Actel Software Licenses and Registration System.
Synphony Model Compiler enables easier and more reliable FPGA execution of algorithms by offering a more automated implementation and verification flow for engineers using MATLAB/Simulink.
The software tool achieves significantly higher productivity than alternative MATLAB/Simulink flows and gives the designer a mechanism to quickly evaluate high-level area and performance trade-offs. Synphony Model Compiler supports many of Microsemi's FPGAs, including the RTAX-DSP, RTAX-S/SL, Axcelerator, as well as the ProASIC3, IGLOO, and Fusion devices.
Synphony Model Compiler delivers performance and productivity benefits for designers who are implementing DSP circuits into FPGAs. For algorithm designers, the software offers advanced high-level synthesis in their chosen design environment and automates a smooth transition into the Synopsys FPGA logic implementation flow.
For the hardware engineer, the software eliminates costly iterations normally required to create optimum RTL from the DSP algorithm design intent, because it generates the necessary RTL code and offers built-in optimizations that account for device-specific features.
Included in the software:
* A synthesizable IP model library for the MATLAB/Simulink environment for wireless, multimedia and signal processing applications.
* High-level synthesis to automatically produce a bit-exact, optimized HDL implementation.
* An automated flow to capture test vectors from the high-level model.
* Automatic HDL test bench generation to verify bit accuracy.
* Creation of C-models representing the final RTL for use in hardware and software verification flow (optional package required).
* Integration with Synplify Pro logic synthesis for efficient FPGA implementation.
"Microsemi devices offer significant value in integration, performance and flexibility for designers of electronic systems. However, design teams need faster and more productive ways to get the most out of these devices," said Chris Eddington, product marketing director at Synopsys.
"Synphony Model Compiler enables engineers to explore and implement their ideas much more quickly and from higher levels of abstraction than traditional HDL flows. By collaborating with Microsemi's SoC Products Group on high-level design flows like Synphony Model Compiler, we can deliver much greater design and verification productivity to our mutual customers."
"The RTAX-DSP family of DSP-enabled space flight FPGAs combine the advantages of efficient integration of DSP algorithms with high levels of tolerance to the damaging effects of radiation encountered in space," states Ken O'Neill, director of high reliability product marketing at Microsemi's SoC Products Group. "Synopsys' Synphony Model Compiler is an important tool in our Libero IDE design suite to efficiently manage and optimize DSP designs."
Synphony Model Compiler AE licenses are available to Actel customers at no cost. For more information and to receive your free license, visit the Actel Software Licenses and Registration System.
Arasan Chip Systems offers complete solution for UFS IP
SAN JOSE, USA: Arasan Chip Systems Inc., a leading provider of Total Semiconductor IP Solutions, announced that it has been developing the Universal Flash Storage (UFS) IP core, a next generation memory interface being finalized by JEDEC. Arasan has engaged with its strategic lead customers to help them productize this interface.
Anticipating the increasing size of embedded code and the requirement to store, share media in consumer electronics and systems, the JEDEC standard's body has embarked on defining a Universal Flash Storage (UFS) standard. This standard is expected to scale in performance and features to span existing and emerging usage models for non-volatile memory.
The UFS standard is based on modular layered protocol architecture. This architecture enables an efficient interface implementation with the ability to scale the interface to meet future performance requirements. Arasan with its domain expertise and involvement with the JEDEC body has been developing a complete IP core solution for UFS - spanning Software, Controller IP, MIPI UniPro Link, and M-PHY IP.
"Implementing a complex memory interface such as UFS requires an in-depth understanding of the UFS specification and architecture," said Prakash Kamath, VP of Engineering at Arasan. "Customers can rely on our UFS IP core, backed by confidence in our expertise, to hasten introduction of their SoCs."
"SoC designers are looking for a common non-volatile memory interface that can support different system architectures while ensuring they have a wide supply of memory chips," added Kamath. "Arasan is committed to keeping our UFS IP in synch with the evolving JEDEC standard, which is scheduled to get ratified in the first half of 2011."
Arasan's high-quality UFS IP core is designed using our rigorous IP design and verification methodology, making Arasan the preferred choice for first time silicon success. Arasan offers a Total IP Solution for the UFS IP consists of RTL IP for the controller, PHY IP, verification IP and a portable software stack - all backed by our World-class customer support.
Anticipating the increasing size of embedded code and the requirement to store, share media in consumer electronics and systems, the JEDEC standard's body has embarked on defining a Universal Flash Storage (UFS) standard. This standard is expected to scale in performance and features to span existing and emerging usage models for non-volatile memory.
The UFS standard is based on modular layered protocol architecture. This architecture enables an efficient interface implementation with the ability to scale the interface to meet future performance requirements. Arasan with its domain expertise and involvement with the JEDEC body has been developing a complete IP core solution for UFS - spanning Software, Controller IP, MIPI UniPro Link, and M-PHY IP.
"Implementing a complex memory interface such as UFS requires an in-depth understanding of the UFS specification and architecture," said Prakash Kamath, VP of Engineering at Arasan. "Customers can rely on our UFS IP core, backed by confidence in our expertise, to hasten introduction of their SoCs."
"SoC designers are looking for a common non-volatile memory interface that can support different system architectures while ensuring they have a wide supply of memory chips," added Kamath. "Arasan is committed to keeping our UFS IP in synch with the evolving JEDEC standard, which is scheduled to get ratified in the first half of 2011."
Arasan's high-quality UFS IP core is designed using our rigorous IP design and verification methodology, making Arasan the preferred choice for first time silicon success. Arasan offers a Total IP Solution for the UFS IP consists of RTL IP for the controller, PHY IP, verification IP and a portable software stack - all backed by our World-class customer support.
1V to 16V hot-swap IC with precision current-sense output
SUNNYVALE, USA: Maxim Integrated Products has introduced the MAX5977, a hot-swap controller for 1V to 16V backplanes. This device features an integrated current-sense amplifier that provides a 1 percent accurate current output over a 10mV to 50mV input voltage range. This allows system designers to precisely monitor/measure load current in high-availability systems.
A calibration mode allows the current-sense amplifier to be fine-tuned for production testing of the design. The MAX5977 is well suited for networking, base station, storage, and computer server line cards requiring high reliability and precision current monitoring.
The MAX5977 allows line cards to be safely inserted and removed from a live backplane without causing glitches on the system power-supply rail. It is rated for 1V to 16V input and can withstand transients or inductive spikes up to 28V. An integrated charge pump drives a low-cost, external n-channel MOSFET. VariableSpeed/BiLevel fault protection improves system reliability by quickly responding to overcurrent and short-circuit conditions, while preventing nuisance trips caused by noise or transient conditions.
The MAX5977A latches off after a fault condition, while the MAX5977B automatically restarts. Other features include: programmable undervoltage and overvoltage protection, an active-high power-good (open-drain) output, and an active-low (open-drain) fault output.
The MAX5977 is packaged in a 20-pin TQFN-EP and is fully specified over the -40 degrees Celsius to +85 degrees Celsius extended temperature range. Prices start at $1.51 (1000-up, FOB USA).
A calibration mode allows the current-sense amplifier to be fine-tuned for production testing of the design. The MAX5977 is well suited for networking, base station, storage, and computer server line cards requiring high reliability and precision current monitoring.
The MAX5977 allows line cards to be safely inserted and removed from a live backplane without causing glitches on the system power-supply rail. It is rated for 1V to 16V input and can withstand transients or inductive spikes up to 28V. An integrated charge pump drives a low-cost, external n-channel MOSFET. VariableSpeed/BiLevel fault protection improves system reliability by quickly responding to overcurrent and short-circuit conditions, while preventing nuisance trips caused by noise or transient conditions.
The MAX5977A latches off after a fault condition, while the MAX5977B automatically restarts. Other features include: programmable undervoltage and overvoltage protection, an active-high power-good (open-drain) output, and an active-low (open-drain) fault output.
The MAX5977 is packaged in a 20-pin TQFN-EP and is fully specified over the -40 degrees Celsius to +85 degrees Celsius extended temperature range. Prices start at $1.51 (1000-up, FOB USA).
Sofics, ICsense merge ESD and I/O technologies
GISTEL & LEUVEN, BELGIUM: Sofics bvba of Gistel, a leading provider of ESD solutions for ICs, and ICsense of Leuven, a prominent designer of analog, mixed-signal, and high-voltage ICs and turnkey ASICs, have partnered to create the world’s first integrated ESD and I/O design solution to allow a stable, fully protected I/O of 3.3V with 1.8V transistors in a TSMC 40nm process.
IP for the novel, patented design is available now. It provides a general-purpose I/O pad that can interface with legacy off-chip components and devices including SIMs and DDR and SDXC memory which are used in WIFI, GPS, and Bluetooth, and other wireless devices, and in advanced multimedia interfaces such as HDMI, USB 3.0, and SATA. A TSMC 28nm version is under development.
The technology was originally developed for the Livanto ICE8060 baseband IC from Icera Inc., the leading supplier of soft modem chipsets for smartphones, tablets and mobile broadband devices. This device is now in production.
“We wanted true 3.3V signalling on our new baseband chip without the extra cost of 2.5V/3.3V masks,” said Peter Hughes, Icera Vice President of Silicon Engineering and Operations. “By integrating ESD protection with high-voltage capability, the Sofics/ICsense team gave us the ability to safely handle off-chip interfaces up to 3.6 volts with 1.8-volt internal transistors. The design worked right the first time.”
According to Sofics CEO Koen Verhaege his company and ICsense worked in close collaboration to achieve these results. “Our TakeCharge technology contributed full ESD protection up to 4kV HBM and 300V MM while reducing the silicon footprint of the I/O pads,” he said.
Bram De Muer, ICsense CEO, agreed that close collaboration between an ESD expert and an analog IC design specialist was crucial to meeting the challenge of designing the custom I/O. “ICsense used our high-voltage-in-low-voltage expertise to achieve tolerances of -0.3V to 3.9V. This allows chips to communicate reliably under a wide range of start-up and power scenarios, with robust ESD protection.
“It’s a truly integrated technology, incorporating the best of both disciplines.”
IP for the novel, patented design is available now. It provides a general-purpose I/O pad that can interface with legacy off-chip components and devices including SIMs and DDR and SDXC memory which are used in WIFI, GPS, and Bluetooth, and other wireless devices, and in advanced multimedia interfaces such as HDMI, USB 3.0, and SATA. A TSMC 28nm version is under development.
The technology was originally developed for the Livanto ICE8060 baseband IC from Icera Inc., the leading supplier of soft modem chipsets for smartphones, tablets and mobile broadband devices. This device is now in production.
“We wanted true 3.3V signalling on our new baseband chip without the extra cost of 2.5V/3.3V masks,” said Peter Hughes, Icera Vice President of Silicon Engineering and Operations. “By integrating ESD protection with high-voltage capability, the Sofics/ICsense team gave us the ability to safely handle off-chip interfaces up to 3.6 volts with 1.8-volt internal transistors. The design worked right the first time.”
According to Sofics CEO Koen Verhaege his company and ICsense worked in close collaboration to achieve these results. “Our TakeCharge technology contributed full ESD protection up to 4kV HBM and 300V MM while reducing the silicon footprint of the I/O pads,” he said.
Bram De Muer, ICsense CEO, agreed that close collaboration between an ESD expert and an analog IC design specialist was crucial to meeting the challenge of designing the custom I/O. “ICsense used our high-voltage-in-low-voltage expertise to achieve tolerances of -0.3V to 3.9V. This allows chips to communicate reliably under a wide range of start-up and power scenarios, with robust ESD protection.
“It’s a truly integrated technology, incorporating the best of both disciplines.”
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