Synopsys chosen as primary EDA partner by Hisilicon

MOUNTAIN VIEW, USA: Synopsys Inc. today announced that Hisilicon Technologies Co., Ltd., a worldwide provider of ASICs and solutions for communication network and digital media, and a subsidiary of Huawei Technologies, has established Synopsys as its primary EDA partner across its implementation and verification design flows.

Hisilicon has signed an expanded business agreement to extend its use of Synopsys' IC Compiler place-and-route technology and DesignWare IP as well as other tools from the broad spectrum of Synopsys' Galaxy Implementation and Discovery Verification Platforms.

"Since its founding, Hisilicon has carefully selected the key strategic partnerships that help us deliver high quality ICs and services to our customers," said Teresa He, vice president of Hisilicon Technologies Co. Ltd.

"We chose to partner with Synopsys because of their technology and proven ability to help make us successful. By helping us deploy advanced technologies such as the VMM verification methodology and advanced chip synthesis to improve design and verification productivity, Synopsys has reinforced our confidence in its short- and long-term technical leadership."

"Within a relatively short period of time, Hisilicon has established itself as one of the premier fabless IC design companies in China, and we are grateful to play a supporting role in their success," said John Chilton, senior vice president of marketing and strategic development at Synopsys. "By increasing their usage of Synopsys tools, IP and services, Hisilicon will be able to continue to aggressively focus on bringing differentiated network communications and digital media silicon solutions to market."

With this expanded agreement, Hisilicon has broad access to tools and IP from Synopsys, including the Galaxy Implementation Platform's IC Compiler place-and-route technology, DC Ultra RTL synthesis, DFTMAX compression, Formality power-aware equivalence checking, PrimeTime SI signal integrity analysis, PrimeTime PX power analysis and StarRC parasitic extraction; the Discovery Verification Platform's VCS with MVSIM voltage-aware simulator and HSPICE circuit simulator, and MVRC voltage-aware static rule checker; System Studio algorithm design and analysis; and DesignWare IP for PCI Express 2.0, SuperSpeed USB 3.0 and DDR2/3.