IC packaging innovation increasingly replacing Moore’s Law in mobile electronics competition

SAN JOSE, USA: Smart phones, tablets, e-readers and other mobile applications are increasingly replacing PCs as the key drivers of the semiconductor industry. Consequently, IC packaging innovations that deliver high performance applications in a low-profile, low-cost, and low power design are competing with next node processing technologies as the critical platform for competition in the mobile segment.

OEMs, system developers, foundries, packaging and test subcontractors, chip manufacturers, and fabless chip companies are placing high-risk, high-stakes bets on next generation packaging solutions that are more able to deliver “faster, better, cheaper” results than advances in wafer processing. Many of these companies will be discussing their views of the increasing complex and varied IC packaging options at SEMICON West, to be held on July 12-14, 2011 in San Francisco.

The most dramatic developments in IC packaging concern 3D integrated circuits that propose to stack dies and connect through TSVs to deliver improved functionality, power consumption, space efficiency, and bandwidth. The drive for 3D has spawned a whole ecosystem for TSV technologies from industry, academia and research institutes, to equipment and material suppliers.

Silicon interposer (2.5D) technology based upon TSV has become an important technology in this first wave of 3D implementation, but without design standards, test platforms, and roadmaps that link the strategies of memory, MPU, GPU and other chip manufacturers— including foundries and packaging firms-- to a common, achievable vision, the benefits of 3D IC could be illusive.

These and other critical issues in 3D IC will be discussed in the open session, “3D in the Deep Submicron Era” to be held from 1:30-5:00pm at the NorthOne TechXPOT stage on Wednesday, July 13. Hosted by session chairs, Jie Xue, director, Technology & Quality, Cisco Systems and Gamal Rafai-Ahmed, AMD fellow, AMD, the session will feature speakers from Xilinx, SEMATECH, ITRI, Georgia Institute of Technology, Amkor Technology, GLOBALFOUNDRIES, Avago Technologies, Mentor Graphics, Yole Developpment, Renesas, IBM, ASE, imec, Applied Materials, and Qualcomm.

While much has been written about emerging packaging and integration technologies like 3D TSV, a majority of today’s IC market is optimizing and migrating to advanced packaging technologies such as copper wire bonding, cu pillar flip chip, fan-out wafer level packaging, and other proven solutions.

Current trends and developments in these areas will be explored in the session, “Contemporary Packaging: Challenges and Solutions for 40nm and Beyond,” held on Wednesday, July 13 from 10:30am-12:30pm at the NorthTwo TechXPOT. Led by session chairs, Tom Gregorich of MediaTek and Rich Rice of ASE, this session will feature presentations and panel discussions with representatives from GLOBALFOUNDRIES, TSMC, Siliconware Precision Industries (SPIL), Atmel, STATS ChipPAC and Gartner.

Mobile devices are also being transformed by MEMS sensors and devices that leverage advanced packaging technologies and require tight integration with ICs. Session chair, Prof. Dr. Klaus-Dieter Lang, Head of Fraunhofer IZM, will lead the session, “Heterogeneous Integration with MEMS and Sensors” on Tuesday, July 12 from 2:00pm-4:00 pm at the NorthOne TechXPOT. This session explores leading integration technologies and strategies in MEMS featuring speakers from Microsoft, TechSearch International, Fraunhofer IZM, Toshiba, CEA-Leti, Infineon Technologies, Silex Microsystems, NIST, and Analog Devices.

Source: SEMI, USA.