Cadence Encounter digital flow instrumental in tape-out of Samsung 20-nm test chip proves readiness of Cadence Unified digital flow for 20-nm design

SAN JOSE, USA: Cadence Design Systems Inc. announced that technology leader Samsung Electronics Co. Ltd deployed the Cadence unified digital flow, from RTL to GDSII, to tape out a test chip at 20 nanometers.

The Cadence Encounter-based flow and methodology were integrated to address the requirements of Samsung’s advanced 20-nanometer process technology for the test chip. The flow handled IP integration and validation, as well as the complex design rules at 20 nanometers.

This achievement demonstrates Samsung’s design and manufacturing leadership at advanced nodes and the strength of the Cadence unified digital flow to extend to the next advanced node. Furthermore, achieving this milestone shows that key aspects of the design chain—including IP, libraries, foundry enablement, and software—support critical design rules at 20 nanometers.

Working alongside Cadence engineers, Samsung used the Cadence 20-nanometer digital methodology for design and implementation of a project featuring an ARM Cortex-M0 microprocessor and ARM Artisan physical IP. The result is a logic test chip at cutting-edge geometries that sets the bar for 20-nanometer designs.

"Samsung’s successful tapeout of this challenging 20-nanometer design is the result of great collaboration between two industry leaders,” said Chi-Ping Hsu, senior VP, research and development, Silicon Realization Group at Cadence. “Consistent with the EDA360 vision, this effort underscores the need for deep relationships among electronics companies to achieve these types of technology milestones.”

This latest collaboration at 20 nanometers extends the ongoing relationship between Cadence and Samsung on design-for-manufacturing and previous advanced node flows, including the Common Platform’s 32/28-nanometer flow from RTL synthesis to GDSII and signoff for Samsung’s low-power high-k metal gate (HKMG) process technology.

“This tapeout is an extremely important accomplishment for Samsung, and we are incredibly proud of the work our team has done,” said Dr. Kyu-Myung Choi, VP of System LSI infrastructure design center, Device Solutions, Samsung Electronics.

“We knew working at 20 nanometers would pose significant challenges, and we were impressed with how the Cadence Encounter digital flow was able to address the new challenges at this advanced node. Our success speaks for itself—we are very pleased we chose Cadence to help us demonstrate our leadership position at 20 nanometers.”

Cadence products used in the 20-nanometer digital flow include the Encounter Digital Implementation System, Encounter RTL Compiler, Incisive Enterprise Simulator, Encounter Power System, QRC Extraction, Encounter Timing System, Encounter Test and Physical Verification System. The Cadence NanoRoute Router was used for 20-nanometer advanced digital routing.