Real Intent delivers next release of Meridian CDC for clock domain crossing sign-off of SoC designs

USA: Real Intent Inc. announced the Version 5.0 release of its Meridian CDC product for comprehensive clock domain crossing analysis.

This new software release adds enhanced speed, analysis and SystemVerilog language support, maintaining Real Intent’s product leadership in delivering what the company believes is the industry’s fastest-performance, highest-capacity and most precise CDC solution in the market.

Meridian CDC performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC or FPGA devices are received reliably. With a giga-scale capacity, Meridian CDC is the only solution that enables all aspects of CDC sign-off.

Meridian CDC excels in speed and low-noise analysis of asynchronous clock domains in SoC designs, with an enhanced formal engine that now goes even further and faster to find hidden CDC problems. Its design language support now includes the SystemVerilog synthesizable subset.

In addition, Real Intent has substantially enhanced the user experience with a new front-end interface that incorporates the latest Verdi Automated Debug System from Synopsys, and delivers improved analysis setup, debug features and ease of use.

New features of Meridian CDC Version 5.0 include:
* A hierarchical flow that supports partitioned analysis of designs without waivers or sacrifice of top-level full-chip precision to achieve sign-off of giga-scale designs.
* A new correct-by-configuration design setup to enhance analysis and reporting clarity for clock crossings to ease the sign-off process.
* Enriched SDC design constraint support with the addition of set clock groups and naming schemes.
* “Cleaner and meaner” issue reporting for: bus handling; reset analysis, including glitches in both asynchronous and synchronous domains; and crossings that may be blocked by environment definition.
* An enhanced formal analysis engine with greater speed and coverage.
* Significant enhancements to the SystemVerilog support for interface elements.
* Verdi3 integration - the industry-leading debug platform from Synopsys (formerly SpringSoft).