USA: CLK Design Automation announced that MediaTek, Inc. has adopted Variance FX for the generation of timing derates.
Advanced timing derates, such as AOCV and POCV, are an essential part of 28nm and 20nm physical design flows to systematically account for manufacturing process, voltage, and temperature (P/V/T) variance. Systematic margining enhances existing STA and physical optimization tools ability to improve timing closure and design performance.
MediaTek is one of the leaders in the adoption of AOCV and systematic margining methods to deliver high performance SOCs at 28nm and 20nm. CLK Design Automation's Variance FX delivers higher accuracy derates compared with traditional OCV sign-off. Variance FX helps MediaTek to avoid over-design, reduce hold time buffers, and achieve better performance, power, and area.
"With Variance FX, we are working with MediaTek to implement leading edge timing margin analysis," said Isadore Katz, president and CEO of CLK Design Automation. "We've been working closely with MediaTek to build high accuracy derate tables that capture process, temperature, and voltage sensitivity for their 28nm and 20nm libraries to help them deliver high performance designs."
Monday, June 3, 2013
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