FRANCE: Alchimer, S.A., a leading provider of wet deposition technologies for dual damascene, through-silicon vias (TSVs), MEMS and solar, announced a joint development project with imec to evaluate and implement Copper (Cu) filling solutions for advanced nano-interconnect technologies.
The focus will be on Alchimer's Electrografting (eG) product family that has demonstrated void-free filling on 7nm node devices and allows direct Cu fill on barrier with no seed layer required for damascene processes.
As CMOS scaling creates finer features, market requirements for copper damascene include smaller dimensions (≤16/14 nm) with a thin barrier layer, and thin or no Cu seed layer.
Filling processes must be defect/void free to meet reliability specifications, and achieve high yields. Conventional physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes are not meeting these requirements. Alchimer's wet deposition technologies are based on a molecular build-up process that breaks through the limitations of dry deposition processes.
The goal of the JDP is to obtain reliability data and electrical performance for eG wet deposition processes in a 300mm manufacturing environment for sub-22nm technologies. As part of the JDP, the companies will assess the plating chemistry and work to identify the optimal process conditions for 300mm wafer-level advanced damascene plating applications.
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