ARM announces AMBA 5 CHI specification to enable high performance, highly scalable SoC technology

Design Automation Conference 2013, UK: ARM announced the AMBA 5 CHI (Coherent Hub Interface) specification which will enable ARM Cortex-A50 series processors to work together in high-performance, coherent processing “hubs”, and to deliver the high data rates that are common in enterprise markets, such as servers and networking.

Building on the success of AMBA 4 ACE technology, the AMBA 5 CHI specification has been developed by ARM with the participation of leading industry players including ARM semiconductor partners, third party IP providers and the EDA industry. The AMBA 5 CHI protocol is used by the ARMv8 architecture-based Cortex-A57 and Cortex-A53 processors and the CoreLink DMC-520 Dynamic Memory Controller. It is also used by the CoreLink CCN-504 Cache Coherent Network, which is capable of 1 Terabit/s data flows.

AMBA 5 CHI has been developed to support high frequency, non-blocking data transfers between multiple fully coherent processors. The interface ensures optimal system performance by supporting distributed level 3 caches, very high rates of I/O coherent communication, and Quality of Service (QoS) functionality. The AMBA 5 CHI architecture also introduces a layered model to allow implementations to separate communication and transport protocols, which enables the optimal trade-off between performance, power and area.