SiBEAM adopts Azuro CTS for complex multi-mode SoC design

SANTA CLARA, USA: Azuro Inc., a leading provider of advanced clock tree synthesis and timing optimization tools for digital chip design, today announced that SiBEAM has adopted Azuro’s PowerCentric clock tree synthesis (CTS) solution.

“CTS has become one of the critical bottlenecks in physical design. It typically takes a lot of effort to ensure that clocks are balanced correctly across all operating modes and corners," said Bernard Shung, VP of IC Engineering at SiBEAM. “Azuro CTS works directly from the multi-mode sign-off constraints, and delivers superior timing to our current flow with fewer iterations. Azuro’s clock trees are also smaller and lower power too.”

“Modern physical design techniques such as multi-mode, multi-corner, on-chip-variation derates, multi-voltage, and clock gating compound to cripple the ability of traditional CTS tools to deliver efficient clock trees,” said Paul Cunningham, CEO of Azuro. “In particular, it is fundamentally impossible to decompose multi-mode timing constraints into a set of tree-based skew targets. Azuro’s CTS algorithms are graph-based not tree-based and are therefore able to directly solve a true multi-mode clock balancing problem.”