Avago debuts 28-nm ASIC embedded SerDes with industry-leading 30-Gbps performance

DesignCon 2011, SAN JOSE, USA. & SINGAPORE: Avago Technologies, a leading supplier of analog interface components for communications, industrial and consumer applications, announced that it has demonstrated 30-Gbps performance with its new Serializer/Deserializer (SerDes) core in 28-nm process technology.

The company also announced it has shipped over 150 million embedded SerDes channels integrated in Application-Specific Integrated Circuits (ASICs) used for data communication in networking, computing and storage applications. The milestones reflect the growing demand for increased bandwidth for servers, routers and other data center equipment.

Avago will demonstrate 30-Gbps speeds with its 28-nm SerDes in the LeCroy booth (#307) at the DesignCon 2011 exhibition in the Santa Clara Convention Center in Santa Clara, California from February 1-2.

“Cloud computing, virtualization and the proliferation of large video files have data center equipment manufacturers keenly focused on expanding bandwidth,” said Sergis Mushell, principal research analyst at Gartner. “For semiconductor companies, integration and manufacturing prowess are keys to keeping pace with data rate requirements in this space.”

“Avago customers have been well pleased by our ability to deliver first-time-right ASIC silicon, which played a big part in surpassing 150 million SerDes cores shipped,” said Frank Ostojic, VP and GM of the ASIC Products Division at Avago. “We have repeatedly set new industry standards for performance benchmarks with our SerDes cores to help data center equipment OEMs keep up with bandwidth demands.”

In November 2010, Avago announced it was first to demonstrate 28-Gbps SerDes performance in 40-nm Complementary Metal–Oxide–Semiconductor (CMOS) process technology. Avago will also exhibit its 40-nm SerDes in the Tyco Electronics booth (#515) and the Amphenol booth (#101) at DesignCon 2011.

Avago Intellectual Property (IP) SerDes cores can be easily integrated due to their modular, multirate architecture. Avago is able to integrate up to 400 SerDes channels or over 190 million gates on a single ASIC, with transistor counts in excess of 4 billion. The Avago SerDes cores feature a unique decision feedback equalization (DFE) architecture, resulting in a number of key performance differentiators such as low overall power, best-in-class data latency, and best-in-class jitter and crosstalk tolerance.