STARC advances test of low power ICs using Mentor's Tessent TestKompress

WILSONVILLE, USA: Mentor Graphics Corp. announced that the Semiconductor Technology Academic Research Center, STARC, has successfully employed the Tessent TestKompress product to expand its low power IC test methodology for ICs used in battery-powered mobile devices and other power-sensitive products.

Using Mentor Graphics technology, STARC is able to detect bridge and small delay failures and to prevent IR drop and power noise in nanometer devices, while minimizing test time and IC power consumption during test.

“The combination of Mentor tools and application expertise was of critical value in our efforts to solve these significant challenges,” said Takashi Aikyo, Senior Manager, Test and Diagnosis Group Development Department-2 at STARC, the semiconductor research consortium located in Yokohama.

“Using standard power format-directed scan chain insertion and unique pattern generation algorithms, TestKompress helped us achieve an ideal combination of highly compressed patterns to reduce test time, and efficient multi-domain test controls to minimize power during test. Using TestKompress, we were able to achieve test compression of 100X with a toggle rate under 20% in order to meet our test quality and power budget requirements, while staying with our manufacturing test
cost constraints.”

“Tessent TestKompress has been successful in a wide variety of low-power IC test applications,” said Greg Aldrich, Director of Marketing for the Silicon Test Solutions product group at Mentor Graphics.

“Its inherently efficient test pattern generation technology—combined with special features to minimize switching activity and manage multiple test domains—makes it the most capable solution available for low power as well as general IC test.”