Aldec adds Mirror-Box debugging technology to hardware-assisted simulation platform

TOKYO, JAPAN: Aldec Inc., a pioneer in mixed HDL language simulation and hardware-based assisted verification solutions for FPGA and ASIC designs, announces the release of a new debugging technology called Mirror-Box™ to the HES™ platform.

“As a technology-leader in the electronic design verification industry, Aldec is committed to meeting the growing needs of verification engineers by adding new debugging technologies like Mirror-Box. The ability for engineers to quickly validate and compare differences between simulation model and actual hardware without rerunning Synthesis and P&R increases their overall productivity in debugging,” said Dave Rinehart, VP of Aldec.

Mirror-Box debugging technology
As designs become more complex and chip density grows, functional verification becomes increasingly overwhelming and time-consuming. To help verification engineers reduce their verification cycles, and in order to meet tight time-to-market deadlines, Aldec adds the Mirror-Box debugging technology to streamline debugging during hardware-assisted simulation.

The Mirror-Box technology allows any component, at any hierarchical level, to be mirrored such that two implementations of the same component can be simulated: one implementation is the original RTL code which resides in the HDL Simulator and the other is its FPGA counterpart which resides in the hardware board.

Mirror-Box benefits:
Time savings - Verification engineer can switch between RTL code and FPGA hardware models without having to rerun Synthesis and Place and Route. This eliminates the need to rebuild the FPGA several times during debugging, which ultimately helps in detecting more errors and bugs per day.

In-hardware validation - Runtime comparison of component outputs between RTL code and actual hardware, allowing detection of discrepancies between the simulation model and real hardware.

Flexibility - Verification engineer can make changes to the design component selected as Mirror-Box in HDL simulator while the rest of the design runs in the FPGA hardware.