Adesto wins DARPA award to develop sub-threshold non-volatile, embedded CBRAM memory

SUNNYVALE, USA: Adesto Technologies, the leading developer of CBRAM, a low power and low cost CMOS non-volatile memory, has received an award from DARPA to develop and demonstrate CBRAM memory devices that operate at sub threshold voltages – a level that is more than 100 times lower than standard Flash memory.

A successful demonstration of the CBRAM technology could lead to groundbreaking memory and microcontroller devices that consume orders of magnitude lower power.

“We are thrilled to be selected by DARPA in this new endeavor to build and demonstrate a memory device that consumes power at a fraction of today’s memory,” said Narbeh Derhacobian, the CEO of Adesto Technologies. He added, “The DARPA effort when combined with our current development to make CBRAM economical and pervasive could have a dramatic impact on future mobile and embedded devices.”

Adesto Technologies develops CBRAM non-volatile stand alone memory devices and IP for embedding in a wide range of semiconductors. Recently, the company enhanced its leadership position in the emerging non-volatile memory market with the acquisition of key patents and IP related to CBRAM technology from Qimonda.

In addition, Adesto announced the formation of a manufacturing partnership with Altis Semiconductor which will lead to the introduction of the first CBRAM product in 2011.

“Throughout my career I have evaluated many low power technologies and found CBRAM to have the potential to reshape microelectronics in a number of areas,” said Michael Fritze, director of Disruptive Electronics at the Information Sciences Institute.

In addition to working with DARPA on sub-threshold non-volatile memories, Adesto has partnered with Professor Ben Calhoun of the University of Virginia to combine CBRAM with low voltage microelectronic circuits that he and his colleagues are developing in order to build ultra low power MCUs and SoCs.

“Adesto’s CBRAM is an outstanding memory technology that we can easily integrate with our ultra low voltage MCUs and SOCs in a standard CMOS process,” said Ben Calhoun, Professor Ben Calhoun at the University of Virginia. “We intend to demonstrate complete solutions within the next year.”