Synopsys' DesignWare STAR memory system shipped in 1 billion chips

MOUNTAIN VIEW, USA: Synopsys Inc. announced that its DesignWare STAR Memory System has shipped in one billion chips from semiconductor manufacturers worldwide, reinforcing its status as a trusted test and repair solution for embedded memories.

The STAR Memory System is an advanced built-in-self-test (BIST) solution that provides automated pre- and post-silicon memory test, debug and diagnostic capabilities. The automated BIST insertion and advanced repair features reduce design integration time and overall design cost while improving test quality.

"The diagnostic capabilities of Synopsys' STAR Memory System gives us the ability to lower our test costs and improve our manufacturing yield," said Dragos Botea, DFT manager at SandForce, Inc. "We need a robust, yet economical, integrated test and repair solution to achieve our yield targets and strict quality objectives for our solid state drive processors. The STAR Memory System provides us with the ability to achieve these goals and helps us meet our shrinking product development cycle."

The increasing memory content in system-on-chips (SoCs) is driving the need for high-quality testing to cover all types of memory defects. The STAR Memory System is a complete and cost-effective solution that embeds on-chip memory test and repair logic in SoC designs and can reduce design integration time from months to weeks.

Coupled with Synopsys' comprehensive synthesis-based test solution, which also includes TetraMAX ATPG and DFTMAX compression for power-aware scan test, DesignWare SerDes IP with built-in self-test and Yield Explorer for yield analysis, the STAR Memory System, when used in conjunction with DFTMAX compression for logic test, further minimizes the impact on design performance, cost and schedule while meeting overall test cost and quality goals. Enhanced test algorithms provide comprehensive out-of-box fault coverage for advanced process nodes, virtually eliminating test escapes that are typical with generic algorithms.

The STAR Memory System can be used with repairable or non-repairable embedded memories for any foundry or process node to address a broad range of design requirements. Its performance-optimized architecture combined with automated hierarchical embedded test and repair logic insertion and integration capability gives designers ease-of-use and increased productivity in achieving their performance, power, area and test goals.

Designers optimize the trade-off between area and advanced diagnostics without sacrificing performance or manufacturing test quality. In addition, advanced transient error fault tolerance enables SoC designers to efficiently address high field-reliability and safety requirements for mission-critical applications.

"With the increasing complexity of integrated circuits and a significant number of memory instances on chips, SoC designers need an integrated memory test and repair system to identify and resolve manufacturing faults," said John Koeter, vice president of marketing for IP and systems at Synopsys. "The broad adoption of Synopsys' silicon-proven STAR Memory System demonstrates the success our customers have had in using the solution to enable high-yielding, memory-rich chips."