Optomec's 3D semiconductor packaging solution profiled in Chip Scale Review

ALBUQUERQUE, USA: Optomec announced today that Chip Scale Review Magazine published an article titled “Jetting Your Way to Fine-pitch 3D Interconnects” in their Sept/Oct 2010 issue.

The article discusses how fine line 3D interconnects can be printed on multi-function stacked die using the Aerosol Jet process. System in Packages (SiP) produced through this process pack more functionality into a smaller footprint which is ideal for mobile devices such as Smartphones and Tablets.

As more chips are stacked into an SiP, the required number and density of interconnects increases creating challenges for traditional methods such as wire bonding.

The article explains how Optomec and Vertical Circuits have partnered to develop a viable production solution that solves this problem. High initial yields with robust electrical performance have been demonstrated using the Aerosol Jet process, and customer devices are currently undergoing the final stages of reliability testing.

Mike O’Reilly, Aerosol Jet Product Manager, states: “In the semiconductor packaging industry, 3D printed interconnects can provide real cost and functional benefits for the production of multi-chip stacked die in System in Package (SiP) applications. Aerosol Jet’s fine line printing capabilities enable significant pitch reductions, thereby increasing interconnect densities and affording greater semiconductor packaging functionality at a fraction of the cost of TSV technology.

“Aerosol Jet’s ability to use off-the-shelf materials and print in normal atmospheric conditions greatly reduces equipment and maintenance costs.”