Synopsys' IC Validator completes qualification for TSMC's 40-nm and 65-nm iDRC/iLVS physical verification

MOUNTAIN VIEW, USA: Synopsys Inc. announced that its IC Validator physical verification product is qualified for TSMC's 40-nm and 65-nm interoperable DRC/LVS runsets, and is immediately available to TSMC customers.

IC Validator, part of the Galaxy Implementation Platform, is an ideal add-on to IC Compiler for In-Design physical verification. By enabling physical verification within the implementation flow, IC Validator enables place and route engineers to accelerate time to tapeout and improve manufacturability.

TSMC's qualification of IC Validator brings the unique advantages of the In-Design flow to the broad range of design teams utilizing TSMC's 40-nm and 65-nm process technologies.

"The iDRC and iLVS format, a key component of TSMC's Open Innovation Platform initiative, allow us to streamline design rule development and deployment, ensuring consistent interpretation across EDA partners and timely availability for our customers," said Suk Lee, director of design infrastructure marketing at TSMC.

"Having successfully completed our rigorous qualification process, Synopsys' IC Validator is now a qualified solution for our 40-nanometer and 65-nanometer process technologies with immediate iDRC/iLVS runset availability for our common customers."

IC Validator boosts performance by parsing interoperable rule decks into efficient atomic instructions suitable for highly parallel execution. Furthermore, IC Validator leverages its scalable hybrid data and command-processing engine to offer a powerful platform for coding and validating the complex polygon and edge-based rules required for emerging process nodes. IC Validator is production-ready and has been successfully used for tape-outs at leading fabless design companies, semiconductor manufacturers and foundries.

IC Validator and IC Compiler share data models and processing engines, resulting in an integrated In-Design physical verification flow designed to deliver signoff-level accuracy coupled with superior productivity.

Compared to the traditional "implement-then-verify" approaches, the In-Design flow avoids late-stage surprises and mitigates costly iterations between place-and-route and signoff. In-Design physical verification provides functionality such as incremental DRC, automatic error detection and correction, optimal metal-fill insertion and rapid ECO validation, all within the place-and-route environment, enabling physical design engineers to generate manufacturing-clean designs that should pass the final signoff check without difficulty, speeding overall time to tapeout.

"Synopsys supports standardization and interoperability, which enables our customers to achieve higher efficiency," said Antun Domic, senior vice president and general manager, implementation group at Synopsys. "We closely collaborated with TSMC to develop the interoperable file format and qualify IC Validator for TSMC's advanced process technologies. This qualification enables us to bring the proven advantages of In-Design physical verification to a rapidly growing number of design teams working at 65 nanometers and below."