Avago first to 28-Gbps performance with 40nm SerDes

SAN JOSE, USA & SINGAPORE: Avago Technologies announced that it has demonstrated 28-Gbps Serializer/Deserializer (SerDes) performance in 40-nm CMOS process technology.

The milestone equates to higher bandwidth Application-Specific Integrated Circuits (ASICs) that integrate the SerDes Intellectual Property (IP), increasing the speed of data communication for servers, routers and other networking, computing and storage applications.

“Avago has an established track record of setting new performance benchmarks for embedded SerDes IP, which is closely connected to our unmatched execution in delivering first-time-right silicon,” said Frank Ostojic, vice president and general manager of the ASIC Products Division at Avago. “We are already working with key customers on products that will bring this 28-Gbps performance breakthrough to the wired communications market.”

Avago SerDes cores can be easily integrated due to their modular, multirate architecture. Avago is able to integrate more than 200 SerDes channels or over 190 million gates on a single ASIC, with FET counts in excess of 4 billion. The SerDes cores offer unique decision feedback equalization (DFE), resulting in lower overall power usage. Additional key differentiators include best-in-class data latency, noise immunity, jitter, and crosstalk performance.

With over 95 million SerDes channels shipped, Avago has an established history of delivering reliable, high-performance ASICs. Three decades of design experience, state-of-the art hierarchical design methodology, and an IP portfolio covering multiple standards, form the company’s foundation for supplying complex ASICs to the wired communications market.

The broad Avago SerDes portfolio supports the PCI Express, Fibre Channel, XAUI, CEI-11G, 10GBASE-KR, and SFI standards, providing the flexibility to address optical, copper, and backplane applications.