WILSONVILLE, USA: Mentor Graphics Corp. announced its new membership in the German-based European Centre for Power Electronics (ECPE), a European consortium focused on the research, education, technology transfer, and promotion of power electronics globally.
Mentor Graphics is the only electronic design automation (EDA) company represented in this industry-driven research network, comprised of over 150 organizations (75 companies and 76 institutions).
Mentor Graphics was selected as an ECPE member due to its unique expertise in both thermal simulation and test solutions including electronic components power cycling for reliability prediction, as evidenced by its recently announced MicReD® Industrial Power Tester 1500A technology.
The key initiatives of the ECPE are to provide global research on power electronics systems; educate the ECPE member network and electronic engineering industry on advancements via workshops and tutorials; and serve as the “unified voice” for the European power electronics industry.
In contributing to the ECPE, Mentor Graphics will focus on its expertise in thermal simulation and test of electronic systems and power cycling technology, which will provide value to the 150+ organizations in this research network. Member companies of the ECPE, such as ABB, Siemens, Fraunhofer, Bosch, ST Microelectronics, Valeo, Infineon and Daimler, will be able to access, share, and apply knowledge on innovative technologies such as the MicReD Power Tester system.
Dr. John Parry, electronics industry manager for Mentor Graphics Mechanical Analysis Division, has been appointed to represent Mentor Graphics within the ECPE. Parry is active in the electronics market, having served as the general chairman of SEMI-THERM 21 and currently represents Mentor Graphics on the JEDEC committee on global thermal standards for the microelectronics industry.
Friday, August 29, 2014
Coverity announces new partnership with Japan-based distributor OGIS-RI
MOUNTAIN VIEW, USA: Coverity Inc., a Synopsys company, announced a new partnership with OGIS-RI, a Japan-based distributor of IT solutions.
This partnership combines Coverity's award-winning software testing platform, which enables organizations to build quality and security testing early in the Software Development Lifecycle (SDLC), with OGIS-RI's open source license and vulnerability management tool, to further drive the adoption of software testing in Japan.
"Time-to-market pressure has dramatically increased for companies across the globe, and as a result, finding and fixing software quality and security issues at the earliest point in the development cycle is a key business driver," said Steve McDonald, VP of Worldwide Product Sales for Synopsys. "We are excited about partnering with OGIS-RI to extend our reach in the Japanese market to help every software-enabled organization create better software and deliver more value to their customers."
OGIS-RI is a pioneer of object-oriented technology in Japan. The company has provided software engineering professional services with cutting-edge technologies and expertise to various industries, including manufacturing, finance and utilities, for more than three decades.
OGIS-RI's current technology focuses are on service-oriented architecture, open source software and enterprise and cloud integration. In addition, OGIS-RI is a 100-percent subsidiary of Osaka Gas. Co. Ltd, the second-largest gas utility company in Japan, and provides full life cycle support for the IT systems of its parent company.
"OGIS-RI has come to the conclusion that Coverity is the best static code analysis tool for its solutions," said Junzo Suzuki, executive officer, member of the board, head of Services Business Division for OGIS-RI.
"Integrating our open source license and vulnerability management tool, Palamida, into Coverity will allow us to offer customers a comprehensive solution that enables shorter time-to-market and enhanced reliability in software development. We believe that this will bring to customers' development projects greater security and speed than ever before. With its expertise in business, OGIS-RI continues to strive to deliver the value of this solution to customers operating in the embedded/engineering systems area, where Coverity is thriving, as well as to those in new areas such as finance and telecommunications."
This partnership combines Coverity's award-winning software testing platform, which enables organizations to build quality and security testing early in the Software Development Lifecycle (SDLC), with OGIS-RI's open source license and vulnerability management tool, to further drive the adoption of software testing in Japan.
"Time-to-market pressure has dramatically increased for companies across the globe, and as a result, finding and fixing software quality and security issues at the earliest point in the development cycle is a key business driver," said Steve McDonald, VP of Worldwide Product Sales for Synopsys. "We are excited about partnering with OGIS-RI to extend our reach in the Japanese market to help every software-enabled organization create better software and deliver more value to their customers."
OGIS-RI is a pioneer of object-oriented technology in Japan. The company has provided software engineering professional services with cutting-edge technologies and expertise to various industries, including manufacturing, finance and utilities, for more than three decades.
OGIS-RI's current technology focuses are on service-oriented architecture, open source software and enterprise and cloud integration. In addition, OGIS-RI is a 100-percent subsidiary of Osaka Gas. Co. Ltd, the second-largest gas utility company in Japan, and provides full life cycle support for the IT systems of its parent company.
"OGIS-RI has come to the conclusion that Coverity is the best static code analysis tool for its solutions," said Junzo Suzuki, executive officer, member of the board, head of Services Business Division for OGIS-RI.
"Integrating our open source license and vulnerability management tool, Palamida, into Coverity will allow us to offer customers a comprehensive solution that enables shorter time-to-market and enhanced reliability in software development. We believe that this will bring to customers' development projects greater security and speed than ever before. With its expertise in business, OGIS-RI continues to strive to deliver the value of this solution to customers operating in the embedded/engineering systems area, where Coverity is thriving, as well as to those in new areas such as finance and telecommunications."
Mentor Graphics extends Nucleus RTOS
WILSONVILLE, USA: Mentor Graphics Corp. announced a new version of the Mentor Embedded Nucleus real time operating system (RTOS) targeting high-performance, next-generation applications for connected embedded devices.
The Nucleus RTOS process model is expanded to include ARM Cortex M- based cores. For the first time, software developers can use a single embedded operating system to increase system reliability through memory partitioning for the entire spectrum of ARM cores, facilitating code reuse across an entire product family comprising low-end to high-end devices.
New in this release is a multicore framework to manage inter-process communication (IPC) and processor life cycle for complex heterogeneous system-on-chip (SoC) and enhanced Nucleus RTOS graphics capabilities with Imagination and Vivante GPU support.
System developers can now use a real-time operating system that is scalable to conform to resource limitations typical of microcontroller (MCU)-based devices while still providing space partitioning to improve system reliability.
By using the memory protection unit (MPU) on ARM Cortex M- based cores, the Nucleus RTOS process model creates memory partitioning without the need to implement virtual memory, maintaining a lightweight operating environment that can be executed in devices with limited memory by “executing in place” out of flash devices. The Nucleus RTOS process model improves system reliability for devices with aggressive dependability requirements, and for devices with safety requirements such as those designed for industrial and medical devices.
Today’s complex SoC architectures combine application-class and microcontroller-class cores, driving the consolidation of heterogeneous operating environments on to a single device. To address these complexities Nucleus RTOS includes the Mentor Embedded Multicore Framework (MEMF) for asymmetric multi-processing (AMP) enablement.
Based on a clean-room implementation of the functionality in “virtIO”, “remoteproc”, and “rpmsg”, MEMF enables developers to integrate Nucleus RTOS, Linux®, and bare metal-based applications and manage the challenges associated with IPC, resource sharing, and processor control within a heterogeneous multi-OS environment. Developers can control the boot-up and shut-down of individual cores on a SoC, allowing applications to maximize compute performance or minimize power consumption based on the use case.
The Nucleus RTOS process model is expanded to include ARM Cortex M- based cores. For the first time, software developers can use a single embedded operating system to increase system reliability through memory partitioning for the entire spectrum of ARM cores, facilitating code reuse across an entire product family comprising low-end to high-end devices.
New in this release is a multicore framework to manage inter-process communication (IPC) and processor life cycle for complex heterogeneous system-on-chip (SoC) and enhanced Nucleus RTOS graphics capabilities with Imagination and Vivante GPU support.
System developers can now use a real-time operating system that is scalable to conform to resource limitations typical of microcontroller (MCU)-based devices while still providing space partitioning to improve system reliability.
By using the memory protection unit (MPU) on ARM Cortex M- based cores, the Nucleus RTOS process model creates memory partitioning without the need to implement virtual memory, maintaining a lightweight operating environment that can be executed in devices with limited memory by “executing in place” out of flash devices. The Nucleus RTOS process model improves system reliability for devices with aggressive dependability requirements, and for devices with safety requirements such as those designed for industrial and medical devices.
Today’s complex SoC architectures combine application-class and microcontroller-class cores, driving the consolidation of heterogeneous operating environments on to a single device. To address these complexities Nucleus RTOS includes the Mentor Embedded Multicore Framework (MEMF) for asymmetric multi-processing (AMP) enablement.
Based on a clean-room implementation of the functionality in “virtIO”, “remoteproc”, and “rpmsg”, MEMF enables developers to integrate Nucleus RTOS, Linux®, and bare metal-based applications and manage the challenges associated with IPC, resource sharing, and processor control within a heterogeneous multi-OS environment. Developers can control the boot-up and shut-down of individual cores on a SoC, allowing applications to maximize compute performance or minimize power consumption based on the use case.
Worldwide semiconductor market forecasted to be $325 billion in 2014
USA: The World Semiconductor Trade Statistics (WSTS) has released its updated semiconductor market forecast. WSTS predicts that the world semiconductor market will reach $325 billion in 2014, up 6.5 percent from 2013.
All major product categories will show a high single digit growth rate, except microprocessors which will show a soft decline. The growth will be largely driven by smartphones, tablets and automotive.
The highest growth rates are shown for the Analog (9.1 percent) and Sensor (9.1 percent) category. By region, all regions, except Japan, will grow from 2013. Japan market is forecasted to decline from 2013 in US dollar basis due to JPY depreciation compared to 2013.
Solid growth for all product categories is expected to continue over the next two years, under the assumption of macro economy recovery throughout the entire forecast period. Worldwide semiconductor market is forecasted to be up 3.3 percent to $336 billion in 2015. For 2016, the market is forecasted to be $350 billion, up 4.3 percent.
By end market, automotive and communications (especially wireless) are expected to grow stronger than the total market, whereas consumer and computer are assumed to rermain almost flat.
By region, Asia-Pacific will be the fastest growing region and expected to reach $207 billion in 2016, which is almost 60 percent share of the total semiconductor market.
All major product categories will show a high single digit growth rate, except microprocessors which will show a soft decline. The growth will be largely driven by smartphones, tablets and automotive.
The highest growth rates are shown for the Analog (9.1 percent) and Sensor (9.1 percent) category. By region, all regions, except Japan, will grow from 2013. Japan market is forecasted to decline from 2013 in US dollar basis due to JPY depreciation compared to 2013.
Solid growth for all product categories is expected to continue over the next two years, under the assumption of macro economy recovery throughout the entire forecast period. Worldwide semiconductor market is forecasted to be up 3.3 percent to $336 billion in 2015. For 2016, the market is forecasted to be $350 billion, up 4.3 percent.
By end market, automotive and communications (especially wireless) are expected to grow stronger than the total market, whereas consumer and computer are assumed to rermain almost flat.
By region, Asia-Pacific will be the fastest growing region and expected to reach $207 billion in 2016, which is almost 60 percent share of the total semiconductor market.
Full compliance with military temperature specification planned for Altera 20 nm FPGA and SoC devices
SAN JOSE, USA: Altera Corp. announced military temperature (Mil Temp) qualification plans for its newest 20 nm Arria 10 FPGAs and SoCs, which will be qualified for extreme temperature environments (-55C to 125C ambient).
In addition to the ratings, Altera can provide guidelines on speed grades, protocols, and external memory interfaces best suited to specific applications. All devices will be characterized, qualified and tested by Altera, providing reduced and reliable lead times.
“Altera is committed to supporting military customers by ensuring Mil Temp variants of our next-generation products are available,” said David Gamba, senior director of the Military, Aerospace and Government Business Unit at Altera. “Though not all defense applications operate in the extremes of the Mil Temp range, early notification of these qualification plans allows customers to make valuable platform design decisions now that allow for cost-effective variants and easier design migration later.”
Altera’s Arria 10 FPGA and SoC devices are the only FPGAs in the industry to feature integrated, hardened IEEE 754-compliant, floating-point operators, which deliver the industry’s highest GFLOPS per Watt performance compared to other hard floating point solutions on the market. The hard floating point DSP blocks featured in Arria 10 devices facilitate native floating point support, thereby reducing development time by six to 12 months.
These macros are useful for many military and aerospace applications, from real-time tactical uses to wide-view satellite survey platforms. They also enable precise designs in ground-based and airborne phased-array radar and directional antenna applications.
Arria 10 SoCs are also the industry’s only 20 nm devices with integrated ARM processors.
In addition to the ratings, Altera can provide guidelines on speed grades, protocols, and external memory interfaces best suited to specific applications. All devices will be characterized, qualified and tested by Altera, providing reduced and reliable lead times.
“Altera is committed to supporting military customers by ensuring Mil Temp variants of our next-generation products are available,” said David Gamba, senior director of the Military, Aerospace and Government Business Unit at Altera. “Though not all defense applications operate in the extremes of the Mil Temp range, early notification of these qualification plans allows customers to make valuable platform design decisions now that allow for cost-effective variants and easier design migration later.”
Altera’s Arria 10 FPGA and SoC devices are the only FPGAs in the industry to feature integrated, hardened IEEE 754-compliant, floating-point operators, which deliver the industry’s highest GFLOPS per Watt performance compared to other hard floating point solutions on the market. The hard floating point DSP blocks featured in Arria 10 devices facilitate native floating point support, thereby reducing development time by six to 12 months.
These macros are useful for many military and aerospace applications, from real-time tactical uses to wide-view satellite survey platforms. They also enable precise designs in ground-based and airborne phased-array radar and directional antenna applications.
Arria 10 SoCs are also the industry’s only 20 nm devices with integrated ARM processors.
Synopsys DesignWare USB 3.0 IP shipped in over100 million production SoCs
MOUNTAIN VIEW, USA: Synopsys Inc. announced that its DesignWare USB 3.0 Controller and PHY IP has shipped in more than 100 million production system-on-chips (SoCs) used in mobile computing, digital home and cloud computing applications such as smartphones, tablets, set-top boxes, digital TVs, gaming systems and servers.
More than 60 companies have successfully integrated silicon-proven DesignWare USB 3.0 IP into their products' SoCs, including SoCs in the Microsoft XBOX One. This broad usage demonstrates the quality of the IP and how Synopsys enables rapid adoption of the standard. To help ensure interoperability and lower designers' integration risk, the DesignWare USB 3.0 solution has been certified by the USB-IF through USB compliance testing in plugfests and by third-party labs.
"Based on a long history of close collaboration with Synopsys, we have shipped hundreds of millions of products that incorporate Synopsys' DesignWare USB 2.0 and 3.0 IP. In the last year alone, tens of millions of units were shipped globally," said Sanghyun Lee, VP of digital IP development team, System LSI Business at Samsung Electronics. "By using Synopsys' DesignWare USB 3.0 IP, Samsung can deliver leading SoC products to our customers."
"Our SoCs for digital home, networking and WiFi applications ship in very high volumes, so we need high-quality, highly reliable USB 3.0 IP to help ensure our success," said Yee-Wei Huang, VP and spokesman at Realtek. "We chose DesignWare USB 3.0 IP because Synopsys has a track record of delivering certified IP that has undergone extensive third-party interoperability testing. Synopsys consistently delivers high-quality IP that supports advanced power-saving standards, enabling us to reduce power consumption in our wireless SoCs. Integrating DesignWare USB 3.0 IP reduced our design risk, accelerated our time-to-market and assured the high performance that our customers expect."
"Success in high-performance USB graphics solutions demands that we deliver SoCs with the most advanced technology on schedule," said John Cummins, senior VP, worldwide sales and marketing at DisplayLink. "We selected Synopsys DesignWare USB 3.0 IP because we were extremely confident that the IP would deliver the performance, power and area we needed. DisplayLink SoCs that integrate Synopsys USB 3.0 IP are now found in the world's leading manufacturers of docking stations."
Synopsys' complete USB 3.0 IP solution, including controllers, PHYs, verification IP, IP Prototyping Kits and IP Virtual Development Kits, reduces design risk and accelerates IP prototyping, software development and integration. The DesignWare USB 3.0 IP has been certified by the USB-IF standards body more than 80 times for both Synopsys and its customers, ensuring interoperability with billions of USB-enabled devices worldwide.
In addition to supporting SuperSpeed, High-Speed, Full-Speed and Low-Speed USB modes, the DesignWare USB 3.0 IP enables 5.0 Gbps SuperSpeed USB data transfer rates while lowering overall power consumption for mobile SoC designs. Synopsys DesignWare USB 3.0 PHY IP is available for more than 25 process technologies from 130-nm to 14/16-nm FinFET, supporting all leading foundries.
More than 60 companies have successfully integrated silicon-proven DesignWare USB 3.0 IP into their products' SoCs, including SoCs in the Microsoft XBOX One. This broad usage demonstrates the quality of the IP and how Synopsys enables rapid adoption of the standard. To help ensure interoperability and lower designers' integration risk, the DesignWare USB 3.0 solution has been certified by the USB-IF through USB compliance testing in plugfests and by third-party labs.
"Based on a long history of close collaboration with Synopsys, we have shipped hundreds of millions of products that incorporate Synopsys' DesignWare USB 2.0 and 3.0 IP. In the last year alone, tens of millions of units were shipped globally," said Sanghyun Lee, VP of digital IP development team, System LSI Business at Samsung Electronics. "By using Synopsys' DesignWare USB 3.0 IP, Samsung can deliver leading SoC products to our customers."
"Our SoCs for digital home, networking and WiFi applications ship in very high volumes, so we need high-quality, highly reliable USB 3.0 IP to help ensure our success," said Yee-Wei Huang, VP and spokesman at Realtek. "We chose DesignWare USB 3.0 IP because Synopsys has a track record of delivering certified IP that has undergone extensive third-party interoperability testing. Synopsys consistently delivers high-quality IP that supports advanced power-saving standards, enabling us to reduce power consumption in our wireless SoCs. Integrating DesignWare USB 3.0 IP reduced our design risk, accelerated our time-to-market and assured the high performance that our customers expect."
"Success in high-performance USB graphics solutions demands that we deliver SoCs with the most advanced technology on schedule," said John Cummins, senior VP, worldwide sales and marketing at DisplayLink. "We selected Synopsys DesignWare USB 3.0 IP because we were extremely confident that the IP would deliver the performance, power and area we needed. DisplayLink SoCs that integrate Synopsys USB 3.0 IP are now found in the world's leading manufacturers of docking stations."
Synopsys' complete USB 3.0 IP solution, including controllers, PHYs, verification IP, IP Prototyping Kits and IP Virtual Development Kits, reduces design risk and accelerates IP prototyping, software development and integration. The DesignWare USB 3.0 IP has been certified by the USB-IF standards body more than 80 times for both Synopsys and its customers, ensuring interoperability with billions of USB-enabled devices worldwide.
In addition to supporting SuperSpeed, High-Speed, Full-Speed and Low-Speed USB modes, the DesignWare USB 3.0 IP enables 5.0 Gbps SuperSpeed USB data transfer rates while lowering overall power consumption for mobile SoC designs. Synopsys DesignWare USB 3.0 PHY IP is available for more than 25 process technologies from 130-nm to 14/16-nm FinFET, supporting all leading foundries.
Renesas announces 40 nm RH850/C1x series of MCUs for HEV/EV motor control apps
SANTA CLARA, USA: Renesas Electronics Corp. announced the new RH850/C1x Series of 32-bit microcontrollers (MCUs), designed for motor control in hybrid electric vehicles (HEVs) and electric vehicles (EVs). Based on Renesas Electronics’ 40-nanometer (nm) process, the RH850/C1x Series features the RH850/C1H and RH850/C1M MCUs, which enable embedded designers to enhance efficiency, reduce system costs, and achieve higher safety levels for HEV/EV motor control systems.
"Awareness of the vehicle’s environmental footprint is increasing, and HEV/EV designers are seeking ways to deliver even better performance, which requires new and more precise motor control systems," said Amrit Vivekanand, VP of automotive, Renesas Electronics America Inc. "The Renesas RH850/C1x MCU series integrates large flash memory capacity, robust motor control peripherals, and single/dual motor control options needed to support the required fine-grained motor control and functional safety for next-generation HEVs and EVs."
The new RH850/C1x devices can be used with the RAA270000KFT RH850 Family power supply management IC (PMIC), which is currently available in sample quantities. The power management IC integrates into one device all the power supply systems required for MCU operation, two external sensor power supply tracks, and a full complement of monitoring and diagnostic functions, significantly reducing the user burden associated with power supply system design.
Concerns about global warming and regulatory efforts to reduce automotive CO2 emissions are driving demand for new technologies to achieve higher efficiencies. For instance, the Corporate Average Fuel Economy (CAFE) standards are driving OEMS to increase overall fleet miles per gallon (MPG) to 54.5 MPG for cars and light-duty trucks by model-year 2025.
As HEV/EV implementations become more mainstream, higher performance applications will require MCUs with greater processing capabilities for efficient motor control. As the HEV/EV market expands, system designers are challenged to reduce costs and increase performance. By integrating hardware peripherals, dedicated for motor control, into the MCU, designers can reduce overall system costs and meet performance requirements.
HEV/EV systems are now being designed to meet ISO 26262 functional safety standards. This system requirement is driving semiconductor products to incorporate a number of embedded features that allow system designers to meet their safety goals.
"Awareness of the vehicle’s environmental footprint is increasing, and HEV/EV designers are seeking ways to deliver even better performance, which requires new and more precise motor control systems," said Amrit Vivekanand, VP of automotive, Renesas Electronics America Inc. "The Renesas RH850/C1x MCU series integrates large flash memory capacity, robust motor control peripherals, and single/dual motor control options needed to support the required fine-grained motor control and functional safety for next-generation HEVs and EVs."
The new RH850/C1x devices can be used with the RAA270000KFT RH850 Family power supply management IC (PMIC), which is currently available in sample quantities. The power management IC integrates into one device all the power supply systems required for MCU operation, two external sensor power supply tracks, and a full complement of monitoring and diagnostic functions, significantly reducing the user burden associated with power supply system design.
Concerns about global warming and regulatory efforts to reduce automotive CO2 emissions are driving demand for new technologies to achieve higher efficiencies. For instance, the Corporate Average Fuel Economy (CAFE) standards are driving OEMS to increase overall fleet miles per gallon (MPG) to 54.5 MPG for cars and light-duty trucks by model-year 2025.
As HEV/EV implementations become more mainstream, higher performance applications will require MCUs with greater processing capabilities for efficient motor control. As the HEV/EV market expands, system designers are challenged to reduce costs and increase performance. By integrating hardware peripherals, dedicated for motor control, into the MCU, designers can reduce overall system costs and meet performance requirements.
HEV/EV systems are now being designed to meet ISO 26262 functional safety standards. This system requirement is driving semiconductor products to incorporate a number of embedded features that allow system designers to meet their safety goals.
R-Car V2H device offers high-resolution image recognition for safer driver assistance systems
SANTA CLARA, USA: Renesas Electronics Corp. announced the availability of its R-Car V2H, the company's newest system-on-a-chip (SoC) implementing state-of-the-art image recognition technology to support high-resolution surround viewing in advanced driver assistance systems (ADAS).
This is the first R-Car ADAS device from Renesas and includes additional functionality for higher performance, lower power, and improved safety in traditional and emerging self-driving vehicles.
Renesas applied technology from its industry-leading R-Car SoCs for automotive infotainment equipment and added high-performance image recognition and low-power consumption technologies in the development of the R-Car V2H. The R-Car V2H enables embedded system manufacturers to deliver high-resolution surround-view monitoring systems, with multiple cameras, for advanced point-of-view switching. This includes rear-view and surround-view capabilities that expand what is seen by the system to every direction around the vehicle, aiding in driver oversight prevention.
These types of sophisticated systems demand substantially higher processing performance in order to handle the expanded range of image recognition targets and increased processing load imposed by multiple cameras with higher pixel counts. At the same time, there is demand for both functional safety, to maintain high quality and performance, and reduced power consumption. Finally, the rapidly increasing cost of software development creates a need for better development efficiency. The Renesas R-Car V2H addresses all of these requirements in a single-chip solution.
"As a premier supplier of advanced semiconductor solutions to the automotive industry, Renesas is mindful not only of the electronic system requirements of today and tomorrow's automobiles, but also the importance of safety, especially with wider adoption of self-driving vehicles," said Amrit Vivekanand, VP of automotive, Renesas Electronics America Inc.
"The R-Car V2H series delivers the imaging technologies, software tools, and high-speed networking needed to develop robust ADAS systems that contribute to smarter, safer automobiles."
This is the first R-Car ADAS device from Renesas and includes additional functionality for higher performance, lower power, and improved safety in traditional and emerging self-driving vehicles.
Renesas applied technology from its industry-leading R-Car SoCs for automotive infotainment equipment and added high-performance image recognition and low-power consumption technologies in the development of the R-Car V2H. The R-Car V2H enables embedded system manufacturers to deliver high-resolution surround-view monitoring systems, with multiple cameras, for advanced point-of-view switching. This includes rear-view and surround-view capabilities that expand what is seen by the system to every direction around the vehicle, aiding in driver oversight prevention.
These types of sophisticated systems demand substantially higher processing performance in order to handle the expanded range of image recognition targets and increased processing load imposed by multiple cameras with higher pixel counts. At the same time, there is demand for both functional safety, to maintain high quality and performance, and reduced power consumption. Finally, the rapidly increasing cost of software development creates a need for better development efficiency. The Renesas R-Car V2H addresses all of these requirements in a single-chip solution.
"As a premier supplier of advanced semiconductor solutions to the automotive industry, Renesas is mindful not only of the electronic system requirements of today and tomorrow's automobiles, but also the importance of safety, especially with wider adoption of self-driving vehicles," said Amrit Vivekanand, VP of automotive, Renesas Electronics America Inc.
"The R-Car V2H series delivers the imaging technologies, software tools, and high-speed networking needed to develop robust ADAS systems that contribute to smarter, safer automobiles."
Altera releases Quartus II software Arria 10 edition v14.0
SAN JOSE, USA: Altera Corp. released Quartus II software Arria 10 edition v14.0, the industry’s most advanced 20 nm FPGA and SoC design environment.
Altera’s proven Quartus II software delivers the fastest compile times and enables the highest performance for 20 nm FPGA and SoC designs in the industry. Customers can further accelerate their Arria 10 FPGA and SoC design cycles by using the broad portfolio of 20 nm-optimized IP cores included in this latest software release.
Altera’s 20 nm design tools feature the most advanced algorithms and deliver the highest quality of results in the industry. The Quartus II software Arria 10 edition v14.0 provides on average 2X faster compile times compared to the nearest competitor’s 20 nm design software.
This productivity advantage allows customers to shorten design iterations and rapidly close timing on their 20 nm design. The software also enables the highest performance 20 nm designs – providing customers more than a one-speed grade performance advantage over competitive FPGAs.
Included in the latest software release is a full complement of 20 nm-optimized IP cores to enable faster design cycles. The IP portfolio includes standard protocol and memory interfaces, DSP and SoC IP cores.
Altera also optimized its popular best-in-class IP cores for Arria 10 FPGAs and SoCs, which include 100G Ethernet, 300G Interlaken, Interlaken Look-Aside and PCI Express Gen3 IP. When implemented in Altera’s Arria 10 FPGAs and SoCs, these best-in-class IP cores deliver the highest performance in the FPGA industry.
Altera’s proven Quartus II software delivers the fastest compile times and enables the highest performance for 20 nm FPGA and SoC designs in the industry. Customers can further accelerate their Arria 10 FPGA and SoC design cycles by using the broad portfolio of 20 nm-optimized IP cores included in this latest software release.
Altera’s 20 nm design tools feature the most advanced algorithms and deliver the highest quality of results in the industry. The Quartus II software Arria 10 edition v14.0 provides on average 2X faster compile times compared to the nearest competitor’s 20 nm design software.
This productivity advantage allows customers to shorten design iterations and rapidly close timing on their 20 nm design. The software also enables the highest performance 20 nm designs – providing customers more than a one-speed grade performance advantage over competitive FPGAs.
Included in the latest software release is a full complement of 20 nm-optimized IP cores to enable faster design cycles. The IP portfolio includes standard protocol and memory interfaces, DSP and SoC IP cores.
Altera also optimized its popular best-in-class IP cores for Arria 10 FPGAs and SoCs, which include 100G Ethernet, 300G Interlaken, Interlaken Look-Aside and PCI Express Gen3 IP. When implemented in Altera’s Arria 10 FPGAs and SoCs, these best-in-class IP cores deliver the highest performance in the FPGA industry.
Thursday, August 28, 2014
EDA industry revenue rises 4.6 percent for Q1 2014
SAN JOSE, USA: The EDA Consortium (EDAC) Market Statistics Service (MSS) recently announced that the Electronic Design Automation (EDA) industry revenue increased 4.6 percent for Q1 2014 to $1,746.1 million, compared to $1,668.5 million in Q1 2013.
Sequential EDA revenue for Q1 2014 decreased 7.1 percent compared to Q4 2013, while the four-quarters moving average, which compares the most recent four quarters to the prior four quarters, increased by 5.2 percent.
"All regions except Japan enjoyed solid growth in the first quarter of 2014 with Pac Rim averaging over 14 percent growth on a rolling four-quarter basis," said Walden C. Rhines, board sponsor for the EDAC MSS and chairman and CEO of Mentor Graphics. "In particular, CAE and PCB showed positive growth for the quarter."
Companies that were tracked employed 30,440 professionals in Q1 2014, an increase of 3.7 percent compared to the 29,360 people employed in Q1 2013, and up 1.9 percent compared to Q4, 2013.
The complete, quarterly MSS report, containing detailed revenue information broken out by both categories and geographic regions, is available to members of the EDA Consortium.
Revenue by product category
The largest category, Computer Aided Engineering (CAE), generated revenue of $638.6 million in Q1 2014, which represents a 6.6 percent increase compared to Q1 2013. The four-quarters moving average for CAE increased 2.8 percent.
IC Physical Design & Verification revenue decreased to $331.9 million in Q1 2014, a 2.4 percent decrease compared to Q1 2013. The four-quarters moving average increased 7.4 percent.
Printed Circuit Board and Multi-Chip Module (PCB & MCM) revenue of $159.7 million for Q1 2014 represents an increase of 1.6 percent compared to Q1 2013. The four-quarters moving average for PCB & MCM increased 5.4 percent.
Semiconductor Intellectual Property (SIP) revenue totaled $518.1 million in Q1 2014, a 10.2 percent increase compared to Q1 2013. The four-quarters moving average increased 7.4 percent.
Services revenue was $97.7 million in Q1 2014, a decrease of 4.1 percent compared to Q1 2013. The four-quarters moving average increased 3.1 percent.
Revenue by region
The Americas, EDA's largest region, purchased $760.7 million of EDA products and services in Q1 2014, an increase of 7.1 percent compared to Q1 2013. The four-quarters moving average for the Americas increased 5.8 percent.
Revenue in Europe, the Middle East, and Africa (EMEA) was up 7.4 percent in Q1 2014 compared to Q1 2013 on revenues of $296.8 million. The EMEA four-quarters moving average increased 4.9 percent.
First quarter 2014 revenue from Japan decreased 19.3 percent to $209.7 million compared to Q1 2013. The four-quarters moving average for Japan decreased 10.2 percent.
The Asia/Pacific (APAC) region revenue increased to $478.9 million in Q1 2014, an increase of 13.5 percent compared to the first quarter of 2013. The four-quarters moving average increased 14.4 percent.
Sequential EDA revenue for Q1 2014 decreased 7.1 percent compared to Q4 2013, while the four-quarters moving average, which compares the most recent four quarters to the prior four quarters, increased by 5.2 percent.
"All regions except Japan enjoyed solid growth in the first quarter of 2014 with Pac Rim averaging over 14 percent growth on a rolling four-quarter basis," said Walden C. Rhines, board sponsor for the EDAC MSS and chairman and CEO of Mentor Graphics. "In particular, CAE and PCB showed positive growth for the quarter."
Companies that were tracked employed 30,440 professionals in Q1 2014, an increase of 3.7 percent compared to the 29,360 people employed in Q1 2013, and up 1.9 percent compared to Q4, 2013.
The complete, quarterly MSS report, containing detailed revenue information broken out by both categories and geographic regions, is available to members of the EDA Consortium.
Revenue by product category
The largest category, Computer Aided Engineering (CAE), generated revenue of $638.6 million in Q1 2014, which represents a 6.6 percent increase compared to Q1 2013. The four-quarters moving average for CAE increased 2.8 percent.
IC Physical Design & Verification revenue decreased to $331.9 million in Q1 2014, a 2.4 percent decrease compared to Q1 2013. The four-quarters moving average increased 7.4 percent.
Printed Circuit Board and Multi-Chip Module (PCB & MCM) revenue of $159.7 million for Q1 2014 represents an increase of 1.6 percent compared to Q1 2013. The four-quarters moving average for PCB & MCM increased 5.4 percent.
Semiconductor Intellectual Property (SIP) revenue totaled $518.1 million in Q1 2014, a 10.2 percent increase compared to Q1 2013. The four-quarters moving average increased 7.4 percent.
Services revenue was $97.7 million in Q1 2014, a decrease of 4.1 percent compared to Q1 2013. The four-quarters moving average increased 3.1 percent.
Revenue by region
The Americas, EDA's largest region, purchased $760.7 million of EDA products and services in Q1 2014, an increase of 7.1 percent compared to Q1 2013. The four-quarters moving average for the Americas increased 5.8 percent.
Revenue in Europe, the Middle East, and Africa (EMEA) was up 7.4 percent in Q1 2014 compared to Q1 2013 on revenues of $296.8 million. The EMEA four-quarters moving average increased 4.9 percent.
First quarter 2014 revenue from Japan decreased 19.3 percent to $209.7 million compared to Q1 2013. The four-quarters moving average for Japan decreased 10.2 percent.
The Asia/Pacific (APAC) region revenue increased to $478.9 million in Q1 2014, an increase of 13.5 percent compared to the first quarter of 2013. The four-quarters moving average increased 14.4 percent.
Renesas intros IEC 61508 TÜV-certified RX631, 63N safety package
SANTA CLARA, USA: Renesas Electronics Corp. has obtained IEC 61508 (Functional Safety) certification for the RX631, RX63N Safety Package, featuring a robust self-diagnostic software and a safety manual for microcontrollers (MCUs) necessary to implement functional safety in industrial equipment.
An RX631, RX63N Safety Solution Evaluation Kit will be available in September 2014, providing a hardware evaluation board with the RX63N MCU, the evaluation version of the self-diagnostic software library, and a Users Guide.
"Renesas is committed to the quality and the inherent functional safety of our devices, and we understand the complexity that comes with stringent standards like the IEC 61508," said Ritesh Tyagi, VP of marketing, Renesas Electronics America. "Our Functional Safety Package solution provides customers one less thing to worry about, reducing their risk in certifying their own safety solutions and allowing them to focus on their core areas of expertise."
Functional safety has become a growing reality for factories, equipment manufacturers, and automation OEMs to reduce economic losses due to equipment failures production losses, and more importantly threats to personnel safety.
The European Machinery Directive 2006/42/EC1 mandates support for functional safety, and efforts to bring relevant industrial equipment into compliance with functional safety standards such as IEC 61508 have been moving forward. Functional safety is now implemented on multiple industrial equipment such as industrial motor drives, control equipment, industrial networking equipment as well as sensors.
Compliance with the IEC 61508 functional safety standard not only requires system designers to perform tasks referred to as safety analysis, such as failure analysis of safety-related hardware and study of failure diagnostic methods and their diagnostic yields, but also to meet defined regulations aimed at reducing specification and design errors in the development process of safety-related systems that can result in malfunctions. In particular, maintaining conformance at all stages of the software development process is a key issue.
An RX631, RX63N Safety Solution Evaluation Kit will be available in September 2014, providing a hardware evaluation board with the RX63N MCU, the evaluation version of the self-diagnostic software library, and a Users Guide.
"Renesas is committed to the quality and the inherent functional safety of our devices, and we understand the complexity that comes with stringent standards like the IEC 61508," said Ritesh Tyagi, VP of marketing, Renesas Electronics America. "Our Functional Safety Package solution provides customers one less thing to worry about, reducing their risk in certifying their own safety solutions and allowing them to focus on their core areas of expertise."
Functional safety has become a growing reality for factories, equipment manufacturers, and automation OEMs to reduce economic losses due to equipment failures production losses, and more importantly threats to personnel safety.
The European Machinery Directive 2006/42/EC1 mandates support for functional safety, and efforts to bring relevant industrial equipment into compliance with functional safety standards such as IEC 61508 have been moving forward. Functional safety is now implemented on multiple industrial equipment such as industrial motor drives, control equipment, industrial networking equipment as well as sensors.
Compliance with the IEC 61508 functional safety standard not only requires system designers to perform tasks referred to as safety analysis, such as failure analysis of safety-related hardware and study of failure diagnostic methods and their diagnostic yields, but also to meet defined regulations aimed at reducing specification and design errors in the development process of safety-related systems that can result in malfunctions. In particular, maintaining conformance at all stages of the software development process is a key issue.
AMD announces heterogeneous C++ AMP language for developers
USA: AMD in collaboration with Microsoft has announced the release of C++ AMP version 1.2 – an open source C++ compiler which implements version 1.2 of the open specification for C++ AMP, available on both Linux and Windows for the first time.
The release represents another step forward toward AMD’s goal of supporting cross-platform solutions, multiple programming languages and continued contributions to the open source community. The tool, which leverages Clang and LLVM, accelerates productivity and ease of use for developers wishing to harness the full power of modern heterogeneous platforms spanning servers, PCs and handheld devices.
“AMD has a consistent track record of enriching the developer experience, and we’re proud to make the first open source implementation of C++ AMP available to enable greater performance and more power-efficient applications,” said Manju Hegde, corporate VP, Heterogeneous Applications and Solutions, AMD. “The cross-platform release is another step in strengthening AMD’s developer solutions, allowing for increased productivity and accelerated applications through shared physical memory across the CPU and GPU on both Linux and Windows.”
“AMD continues to deliver excellent developer tools for heterogeneous programming. Partnering with AMD to deliver C++ AMP to the Linux and Open Source communities was a natural step for Microsoft as we work to improve the performance and developer experience on modern computing platforms,” said S. Somasegar, corporate VP of the Developer Division at Microsoft.
C++ AMP version 1.2 enables C++ developers to accelerate applications across a broad set of hardware and software configurations by supporting three outputs:
* Khronos Group OpenCL[i], supporting AMD CPU/APU/GPU, Intel CPU/APU, NVIDIA GPU, Apple Mac OS X and other OpenCL compliant platforms;
* Khronos Group SPIR, supporting AMD CPU/APU/GPU, Intel CPU/APU and future SPIR compliant platforms; and
* HSA Foundation HSAIL, supporting AMD APU and future HSA compliant platforms.
The release represents another step forward toward AMD’s goal of supporting cross-platform solutions, multiple programming languages and continued contributions to the open source community. The tool, which leverages Clang and LLVM, accelerates productivity and ease of use for developers wishing to harness the full power of modern heterogeneous platforms spanning servers, PCs and handheld devices.
“AMD has a consistent track record of enriching the developer experience, and we’re proud to make the first open source implementation of C++ AMP available to enable greater performance and more power-efficient applications,” said Manju Hegde, corporate VP, Heterogeneous Applications and Solutions, AMD. “The cross-platform release is another step in strengthening AMD’s developer solutions, allowing for increased productivity and accelerated applications through shared physical memory across the CPU and GPU on both Linux and Windows.”
“AMD continues to deliver excellent developer tools for heterogeneous programming. Partnering with AMD to deliver C++ AMP to the Linux and Open Source communities was a natural step for Microsoft as we work to improve the performance and developer experience on modern computing platforms,” said S. Somasegar, corporate VP of the Developer Division at Microsoft.
C++ AMP version 1.2 enables C++ developers to accelerate applications across a broad set of hardware and software configurations by supporting three outputs:
* Khronos Group OpenCL[i], supporting AMD CPU/APU/GPU, Intel CPU/APU, NVIDIA GPU, Apple Mac OS X and other OpenCL compliant platforms;
* Khronos Group SPIR, supporting AMD CPU/APU/GPU, Intel CPU/APU and future SPIR compliant platforms; and
* HSA Foundation HSAIL, supporting AMD APU and future HSA compliant platforms.
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