EDA industry revenue down in Q2-09

SAN JOSE, USA: The EDA Consortium (EDAC) Market Statistics Service (MSS) today announced that the Electronic Design Automation (EDA) industry revenue for Q2 2009 is $1,125.5 million, a 5.6 percent sequential decline from Q1.

On a Q2/Q2 basis, EDA industry revenue declined 15.8 percent to $1,125.5 million, compared to $1,335.9 million in Q2 2008. The four-quarter moving average declined 13.9 percent.

“This recession started with the most precipitous drop in electronics industry history. Nevertheless, the normal pattern of preserving most R&D spending has been maintained by most electronics companies,” said Wally Rhines, EDAC chair and chairman and CEO of Mentor Graphics. “As the electronics industry recovers, and its R&D spending increases to come in line with its growing revenue, the EDA industry would be expected to recover as well.”

Companies that were tracked employed 26,298 professionals in Q2 2009, down 6.1 percent from the 28,004 employed in Q2 2008, and down 1.0 percent from the 26,561 employed in Q1 2009.

Revenue by product category
Computer Aided Engineering (CAE), EDA’s largest category, generated revenue of $449.7 million in Q2 2009. This represents a 12.2 percent decrease over the same period in 2008. The four-quarter moving average for CAE declined 18.6 percent.

In the next largest category, IC Physical Design and Verification, revenue decreased to $270.6 million in Q2 2009, a 12.8 percent decrease compared to Q2 2008. The four-quarter moving average declined 19.7 percent for IC Physical Design & Verification.

Printed Circuit Board and Multi-Chip Module (PCB and MCM) revenue decreased 24.1 percent compared to Q2 2008, to $105.8 million. The four-quarter moving average for PCB and MCM decreased 10.4 percent.

Semiconductor Intellectual Property (SIP) revenue totaled $221.6 million in Q2 2009, a 16.3 percent decrease compared to Q2 2008. The four-quarter moving average for SIP decreased 5.0 percent.

Services revenue was $77.8 million in Q2 2009, a decrease of 28.6 percent compared to Q2 2008. The four-quarter moving average for services increased 7.5 percent.

Revenue by consuming region
The Americas, EDA’s largest region, purchased $509 million of EDA products and services in Q2 2009, representing an 11.5 percent decrease compared to Q2 2008. The four-quarter moving average was down 14.7 percent for the region.

Revenue in Europe, the Middle East, and Africa (EMEA) was down 21.1 percent in Q2 2009 compared to Q2 2008 on revenues of $212.4 million. The four-quarter moving average for EMEA was down 14.3 percent.

Q2 2009 revenue from Japan decreased 21.5 percent to $217.8 million compared to Q2 2008. The four-quarter moving average for Japan decreased 17.9 percent.

The Asia/Pacific (APAC) region decreased to $186.3 million in Q2 2009, a 13.1 percent decrease compared to the same quarter in 2008. The four-quarter moving average declined 5.3 percent.

EDA industry revenue down 10.7pc in Q1-09: EDA Consortium

SAN JOSE, USA: The EDA Consortium (EDAC) Market Statistics Service (MSS) today announced that the electronic design automation (EDA) industry revenue for Q1 2009 declined 10.7 percent to $1192.1 million, compared to $1334.2 million in Q1 2008, driven primarily by an accounting shift at one major EDA company. The four-quarter moving average declined 11.3 percent.

“The business environment remained difficult for EDA as for other industries, with Q1 EDA revenues declining in all regions except Asia Pacific,” said Walden C. Rhines, EDA Consortium chair and Mentor Graphics CEO and chairman. “Nevertheless, for Q1, the overall decline was less than for the previous quarter.”

Companies that were tracked employed 26,561 professionals in Q1 2009, down 2.8 percent from the 27,329 employed in Q1 2008, and down 2.7 percent from the 27,311 employed in Q4 2008.

Revenue by product category
Computer Aided Engineering (CAE), EDA’s largest category, generated revenue of $427.9 million in Q1 2009. This represents an 18.8 percent decrease over the same period in 2008. The four-quarter moving average for CAE declined 16.8 percent.

In the next largest category, IC Physical Design & Verification, revenue decreased to $302.2 million in Q1 2009, a 5.4 percent decrease compared to Q1 2008. The four-quarter moving average declined 21.6 percent for IC Physical Design & Verification.

Printed Circuit Board and Multi-Chip Module (PCB & MCM) revenue decreased 7.1 percent compared to Q1 2008, to $119.9 million. The four-quarter moving average for PCB & MCM decreased 0.6 percent.

Semiconductor Intellectual Property (SIP) revenue totaled $236.3 million in Q1 2009, a 12.8 percent decrease compared to Q1 2008. The four-quarter moving average for SIP decreased 1.4 percent.

Services revenue was $105.7 million in Q1 2009, an increase of 20.4 percent compared to Q1 2008. The four-quarter moving average for services was up 24.6 percent.

Revenue by Consuming Region
The Americas, EDA’s largest region, purchased $494 million of EDA products and services in Q1 2009, representing an 11.6 percent decrease compared to Q1 2008. The four-quarter moving average was down 15.4 percent for the region.

Europe, the Middle East, and Africa (EMEA) revenue was down 15.9 percent in Q1 2009 compared to Q1 2008, with revenues of $223.2 million. The four-quarter moving average for Western Europe was down 7.5 percent.

Q1 2009 revenue from Japan decreased 17.7 percent to $265.5 million compared to Q1 2008. The four-quarter moving average for Japan decreased 10.8 percent.

The Asia/Pacific (APAC) region increased to $209.4 million in Q1 2009, an 11.5 percent increase compared to the same quarter in 2008. The four-quarter moving average declined 4.7 percent.

Indian designers could lead in EDA product development

There will be the multi-nationalization of the product development process, according to Walden C. Rhines, chairman & CEO, Mentor Graphics. More executives recognize that "access to qualified personnel" is the key driver. As per A.T. Kearney Global Services Location Index 2007, India is the most attractive offshoring destination. He was speaking at the Though Leadership Forum organized by the India Semiconductor Association.

Touching on the evolution of EDA, and the role of Indian designers, Rhines said that most electronic engineers did not consider themselves "risk takers". Most electronic engineers also don't like to change tools and fewer even consider "hot" new tools.

On the contrary, young engineers and recent university graduates eagerly adopted new technology. It is a way for them to distinguish themselves, get the productivity advantage and they were less invested in existing methodologies.

Indian designers smart
Comparing Indian designers with the rest of the world, he said that electronic designers in India, on an average, are less experienced than in the United States, Europe and Japan. However, they are on an average, as smart, or smarter, than those in United States, Europe and Japan. There has been an increasing influence of India design centers on the multinational design flows and tools.

Disruptive change creates leadership opportunities. There has been improved power and cost through improved system architecture. The C synthesis enables faster architectural exploration and shorter time to Verilog.

C synthesis matches or exceeds hand coded RTL efficiency, as per STMicroelectronics (Reed-Solomon, Galois Field Multiplier). There have also been system architectural innovations to reduce die size -- Ericsson mobile platforms. There is a need to iterate to find the optimum architecture.

Now, Indian designers have been early adopters of C-based design. The reasons were, one there was a willingness to try new approaches and two, it caused multinational parent companies to accelerate their own adoption.

India is likely to be a leader in transaction level design. They have been able to extract fast, accurate power and timing models from RTL. They have managed runs 100x-1000x faster vs. RTL, retained accuracy at the gate level and RTL, their models run with application software for hardware/software cosimulation, and they have done transaction-based verification using emulation. It has been the same for UPF-compatible verification.

Some other areas of verification where India may lead the way are assertions, coverage based verification, and algorithmic test bench synthesis.

Adoption of place and route technology
Let us see how the adoption of new place and route technology has influenced the industry. When a design flow breaks, what breaks the most often? Place and route breaks every two technology generations. Technology generations ramp to peak volume. Place and route utilizes a semiconductor company's internal software until gate array routers emerge.

Cell-based layout requires hierarchical router with timing. Tangent attacks leading-edge 0.75 micron designs. Later, Cadence became the dominant place and route supplier at 0.35 micron as the fabless industry grew demand. [Cadence acquired Tangent in 1989]. However, at 0.25 microns, SoC drives new technology requirements. This led to the collapse of the FAM business model.

SoC needs "break" the flow. ArcSys emerged at 0.35/0.25 micron. It addresses SoC requirements for large sizes and interconnect delay. It goes public as Avant!, and is later acquired by Synopsys. However, a timing closure crisis emerges at 0.13 micron. Cadence and Avant!/Synopsys try to extend older tool architectures.

Now, timing closure "breaks" the design flow. At this point, Magma emerges at 0.13 micron with timing-driven layout solution. At 90nm, Magma dominates timing-driven design. It also approaches Cadence, Avant!/Synopsys place and route market share. What the industry witnesses is that a new problem emerges and a new, leading-edge solution provider enters every two nodes.

And now, pressures are creating 65/45nm discontinuity. These are process and design variations, low-power requirements, and large design data sizes. Explosive growth in complexity requires multi-corner, multi-mode analysis.

Achieving power/performance design goals requires analysis of corner cases for manufacturing and operational variability. Manufacturing variability multiplies the required corner cases. Hence, manufacturing variability now "breaks" the place and route flow at 65nm. With the advent of 45nm, it demands design for manufacturing (DFM), and ushers in more corners.

Implications for EDA in India
So what are the implications for EDA in this scenario, especially from an Indian context? One, introduce and support leading-edge design tools in India. Two, EDA startups will focus initial sales efforts in San Jose and India. Three, purchasing decisions will increasingly incorporate India design teams to drive flows and decisions. Four, India will emerge as the test bed for new design ideas. As a result, Indian designers would exercise their influence by demanding the best-in-class design tools and capabilities.

Indian designers should always remain open to new design approaches. They should beware of becoming risk adverse as they become more experienced. They should need to stay abreast of the emerging innovations by maintaining close contact with EDA companies, including start-ups. They also need to make EDA suppliers aware of their issues and challenges.