Xilinx, Northwest Logic and Xylon provide low cost FPGA-based MIPI interfaces for video displays and cameras

SAN JOSE, USA: Xilinx Inc. and Northwest Logic and Xylon, Xilinx Premier Alliance Members, announced the availability of a low cost Xilinx FPGA-based MIPI interface IP that is optimized for cost sensitive video displays and cameras.

The MIPI Display Serial Interface (DSI) and Camera Serial Interface 2 (CSI-2) have become the industry connectivity standards for low cost video displays and cameras across a wide variety of embedded systems.

Xilinx FPGAs can now be used to connect image sensors and ASSPs that support the CSI-2 and DSI standards for the development of high bandwidth applications supporting 4K2K and beyond. The release of the support for MIPI furthers Xilinx’s Smarter Vision commitment by now enabling advanced real-time analytics and immersive display applications.

“MIPI DSI and CSI-2 is now the preferred standard for connecting low cost displays, cameras and video-capable application processors to Xilinx® 7 Series and Spartan® 6 FPGAs,” said Aaron Behman, segment lead, broadcast and professional A/V business at Xilinx. “As a result, FPGAs are being incorporated into more MIPI-based products today than ever before, especially in products that support 4K2K and beyond.”

Northwest Logic provides a full range of DSI (Host and Peripheral) and CSI-2 (Tx & Rx) Controller Cores. These cores fully support 1-4 lane and 8 lane (dual 4 lane) MIPI operation. The cores are delivered fully integrated with the PHY logic to implement Xilinx’s low cost MIPI Interface technique.

Xylon provides a broad range of video processing IP Cores. Xylon has taken a Xilinx FPGA Mezzanine Card (FMC), which implements the low cost MIPI Interface approach, Northwest Logic’s CSI-2 and DSI cores and its own cores running on an off-the-shelf Zynq All Programmable SoC evaluation board (ZC702 and ZC706) to create a comprehensive demonstration system.

The demonstration system takes a live video stream from an OmniVision CMOS sensor (OV16820), processes it in a Xilinx FPGA and then streams it to a MIPI-compatible display.