Cadence announces DFI 3.0-compliant design and verification IP

SAN JOSE, USA: Cadence Design Systems Inc. is offering a comprehensive suite of solutions in support of the latest DDR PHY Interface (DFI) 3.0 specification (also announced today by the DFI Technical Group).

Enabling the development of chips and systems to support the emerging DDR4 memory standard, the specification defines an interface protocol between DDR memory controllers and PHYs. Cadence supports the specification across its DDR DRAM Controller IP, DDR PHY IP, and as part of the Cadence Verification IP Catalog. Cadence introduced the industry’s first DDR4 IP memory solution in April of this year.

“Our customers require DFI-compliant design and verification IP that will enable them to be first to market with next-generation SoCs that support the emerging DDR4 standard,” said Marc Greenberg, director of marketing, SoC Realization, Cadence. “Our close working relationship with the DFI Technical Group ensures that we offer integration-ready DFI solutions when the specification becomes available.”

DFI interface adoption continues to rise as designers seek ways to reduce the time-to-market and cost of their SoCs. Cadence has over 400 design wins for DDR controllers and PHYs, and all DDR3 designs currently in development use the DFI interface. This makes DFI 3.0 support critical to customers who must deliver solutions in support of the emerging DDR4 standard.

DFI 3.0
DFI 3.0 defines methods for interfacing to DDR4 devices with proposed data rates up to 3.2 Gbits/second per pin – more than 50 percent faster than the current DDR3 standard – and extends the low-power interface that was introduced with DFI 2.1. By accounting for frequency and power challenges at high speeds, the new standard helps ensure exceptional performance in systems using DDR4 memory.