Nethra Imaging selects Arteris FlexNoC NoC interconnect IP for advanced imaging SoCs

SUNNYVALE, USA: Arteris Inc., a leading supplier of network-on-chip (NoC) interconnect IP solutions, announced that Nethra Imaging has selected its FlexNoC network-on-chip interconnect fabric product and memory scheduler for use in Nethra Imaging's low power, real-time image processing products.

The Nethra Imaging team chose the Arteris FlexNoC interconnect and the Arteris memory scheduler to alleviate wire routing congestion and timing closure issues with many IP blocks communicating simultaneously with DDR memory.

An additional advantage to Arteris FlexNoC's scalable architecture was quality of service (QoS), allowing the Nethra design team to guarantee bandwidth for each IP block and avoid the possibility of dropping pixels. Nethra also benefited from FlexNoC's out-of-the-box support for Tensilica's PIF protocol.

"It only took us two days to evaluate Arteris FlexNoC on our own design," said Ramesh Singh, CEO and president of Nethra Imaging. "We now have a scalable interconnect that can address our foreseeable needs and that can easily adapt to last minute changes to IP or architecture. Furthermore, FlexNoC has allowed us to simplify floor planning and timing closure."

Arteris NoC interconnect IP technology enables SoC designers to achieve lower power, higher memory bandwidth and optimized latencies by individual connections. This improves SoC performance, lowers SoC costs and enables rapid adoption of IPs communicating in a variety of protocols.

The growing Arteris ecosystem provides connectivity to a variety of IPs and IP protocols as well as multiple EDA design flows. Use of the Arteris NoC IP simplifies the front-end design process while easing back-end routing congestion and timing closure issues.

The Arteris FlexNoC product offers ability to reduce the number of interconnect wires required for SoC design. Reducing the number of wires resolves routing congestion at the back-end place-and-route stage, resulting in shorter development cycle time, less SoC complexity, smaller SoC area and less SoC power.