Synopsys' new DesignWare STAR ECC IP helps reduce embedded memory transient errors

MOUNTAIN VIEW, USA: Synopsys Inc. has announced the availability of the DesignWare STAR ECC (Self-Test and Repair Error Correcting Codes) IP as a part of its DesignWare STAR Memory System product family.

The new DesignWare STAR ECC IP offers a highly automated design implementation and test diagnostic flow that helps system-on-chip (SoC) designers to quickly reduce the number of embedded memory transient errors, such as soft errors, that occur in emerging semiconductor process technologies.

Targeted at applications such as automotive, aerospace and high-end computing, the DesignWare STAR ECC IP enables designers to achieve high performance and high field reliability while improving time-to-market.

The DesignWare STAR ECC IP is a configurable IP solution that enables designers to achieve a higher level of protection against transient errors compared to the classic ECC approach and deliver a more reliable product to the market.

This approach allows designers to select the desired level of fault tolerance and generate the corresponding logic through the DesignWare STAR ECC IP. The DesignWare STAR ECC IP is designed to provide optimal performance of partial word writes and improved error detection/correction capability in multi-bit upsets and random bit errors.

"As SoCs manufactured in advanced technology nodes become more susceptible to environmental influences, there is an ongoing need to reduce soft error rates," said John Koeter, vice president of marketing for the Solutions Group at Synopsys.

"The DesignWare STAR ECC IP enables designers to easily select the required fault tolerance level to protect against these transient errors. By using Synopsys' DesignWare STAR ECC IP, designers can achieve their high performance and yield requirements with less risk and improved time-to-market."

The DesignWare STAR ECC IP solution is available now as part of the DesignWare STAR Memory System and works in conjunction with Synopsys' DFTMAX compression to provide a comprehensive test and yield solution for digital logic and embedded memories.