Open-Silicon strengthens patent portfolio with test technology

MILPITAS, USA: Open-Silicon Inc announced that the United States Patent and Trademark Office has issued U.S. Patent 7,805,648 related to Open-Silicon's TestMAX technology.

As a part of Open-Silicon's custom silicon solution, scan-frequency scaling reduces silicon test time providing customers with an additional way to decrease overall device cost.

Introduced in 2009, TestMAX is part of Open-Silicon's MAX Technologies product line – a result of extensive R&D to create a series of products that allow customers to take their designs to a level beyond what the latest EDA tools offer.

As design gate counts continue to grow exponentially, both wafer probe and final test costs increase. TestMAX addresses this challenge by significantly reducing test time, and therefore lowering device cost. Other significant benefits are that it requires no design changes, is scan-architecture independent, and can be applied on previously taped out designs.

Scan-frequency scaling
Traditional scan testing frequencies are limited by the power dissipation in the device under test. By first profiling the scan vectors for power dissipation, Open-Silicon is able to select those tests with lower thermal impact and power mesh currents and greatly increase their frequency.

"The granting of this patent underscores the strength and execution of Open-Silicon's technology solutions," said Colin Baldwin, Director of Marketing at Open-Silicon.

"Fully custom silicon that wins in the market requires a lot more than today's readily-available EDA tools. Our team of experienced engineers is focused on solutions that enable the creation of custom silicon that touts optimal power and performance, while reducing cost and accelerating time-to-market."