KLA-Tencor’s Teron 600 reticle defect inspection platform addresses mask design discontinuities at 2Xnm node

MILPITAS, USA: KLA-Tencor Corp. has introduced the Teron 600 Series reticle (mask) defect inspection systems. Addressing a major transition in mask design at the 2Xnm logic (3Xnm half-pitch memory) node, the new Teron 600 platform will introduce programmable scanner-illumination capability and offer significant improvements in sensitivity and computational lithography power over the current industry-standard platform, TeraScanTMXR.

These advances are necessary to enable development and manufacturing of the innovative reticles that distinguish the 2Xnm node.

Traditionally, mask designers have started with a mask pattern that looks like the target wafer pattern, making small adjustments to the mask features (optical proximity corrections or OPC) until the desired wafer structures are achieved. This approach begins to break down at the 2Xnm node, as a consequence of extending 193nm lithography into an extreme sub-wavelength regime.

Thus, at the 2Xnm node, computational lithography techniques such as Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO) become viable. ILT typically generates a complex mask pattern with an enormous number of very small features, making the mask difficult to manufacture.

To complicate matters even further, Source Mask Optimization (SMO) involves calculating a non-uniform intensity profile for the scanner source. That profile is designed to work together with the ILT mask to deliver the optimum lithographic results on the wafer.

“The dramatic change in reticle strategy for the 2Xnm device generation has created a discontinuity in reticle defect inspection,” remarked Brian Haas, vice president and general manager of the Reticle and Photomask Inspection Division at KLA-Tencor. “The reticle features are much smaller than you would predict from a 3Xnm to 2Xnm shrink. In addition, the mask pattern is so fractured that it is no longer feasible for an engineer to look at the location of a reticle defect and decide whether it is likely to print on the wafer—and potentially cause a catastrophic yield loss in the fab.

"For the 2Xnm node, we must be able to input a custom scanner illumination profile, take into account polarization effects and the photoresist, and rigorously calculate the impact of the reticle defect on the wafer. The Teron 600 leverages KLA-Tencor’s strength in computational lithography and our experience from developing and manufacturing six generations of reticle inspection platforms. As a result it is an extremely high-resolution, low-noise reticle inspection system, equipped for the new 2Xnm challenges. It’s a big achievement for KLA-Tencor, which, we believe, will be tremendously enabling for our customers and the industry.”

The Teron 600 platform has also been designed for flexibility and extendibility. The system has successfully inspected prototype reticles created for ILT / SMO, double-patterning lithography (DPL), and EUV (masks and blanks). The system is engineered to be extendible to potential 1Xnm optical solutions.

Moreover, the Teron 600 Series can work with KLA-Tencor’s TeraScan 500 Series reticle defect inspection systems in a mix-and-match strategy, to provide a cost-effective solution for manufacturing photomask sets that include both critical and non-critical layers.

KLA-Tencor launches 2830 and Puma 9500 Series eDR-5210

MILPITAS, USA: KLA-Tencor Corp. announced two new wafer inspection systems and a new electron-beam review system to address defect issues at the 3Xnm/2Xnm nodes.

The 2830 Series brightfield wafer inspection platform uses a revolutionary high-power plasma light source to illuminate defect types whose size or location made them impossible to detect repeatably before now.

The Puma 9500 Series darkfield wafer inspection platform introduces breakthrough optics and image acquisition technology that give it twice the resolution at twice the speed of its predecessor—allowing the new Puma tools to monitor more layers and more defect types at darkfield speeds.

The eDR-5210 e-beam review and classification system features second-generation electromagnetic-field immersion technology, engineered to deliver extraordinary image quality and actionable defect classification results in a high productivity package.

Each new tool offers substantial benefits over existing technology on its own. In addition, when the new inspection and review systems work interdependently, they can preferentially detect and report yield-relevant defects, enabling fabs to more rapidly identify and remedy complex defect issues at the 3Xnm and 2Xnm nodes.

“While many other equipment companies have been focused on scaling back programs and delaying new platforms during the downturn, KLA-Tencor has continued to invest heavily in developing next-generation products, including two innovative wafer defect inspection systems and an exceptional review tool for the 3Xnm and 2Xnm nodes,” remarked Mike Kirk, Ph.D., vice president and general manager of the Wafer Inspection Group at KLA-Tencor.

“Our customers are introducing complex lithography techniques, new materials and exotic structures. They are coping with additional layers and smaller process windows, and are keenly focused on value. To address these issues, our engineering teams collaborated with suppliers and customers to develop truly innovative technology for the 2830, Puma 9500 and eDR-5210 systems, giving them unprecedented capability. Each of the tools combines substantial advances in performance and throughput.

"Each has the flexibility for use in multiple applications—which adds considerable value in today’s economic environment. Each is designed for extendibility to or from the next device generation, so that fabs can maximize re-use of their investment in capital equipment. We’re confident that together the new inspection and review portfolio represents a big step forward for the industry in overall defect-management ROI: faster detection of excursions, faster resolution of difficult defect issues, and faster time to market for our customers’ next-generation chips.”

The 2830 Series and Puma 9550 Series wafer defect inspection systems and the eDR-5210 e-beam defect review and classification system are backed by KLA-Tencor’s comprehensive service network to maintain their high performance and productivity.

Mentor Graphics: DFM is where all the value is!

As promised, here is the concluding part of my discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

We went over the design for manufacturing (DFM) challenges and how yield can be improved. He also touched upon the design challenges in 45nm and 32nm, respectively.

Given that the semiconductor industry does speak a lot about DFM, what steps are being taken to improve on the overall yield?

According to Sawicki, in the VLSI microchip era, yields started at 60-70 percent, and so DFM wasn't required. However, in the nanochip era, DFM is where all the value is. [VLSI Research.]

Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor GraphicsHe added that at smaller geometries, manufacturing variability has a much greater impact on timing, power dissipation, and signal integrity. Traditional guardbanding is no longer sufficient to guarantee competitive performance at acceptable yields, and excessive design margins erase the advantages sought by going to the next node in the first place.

Moving to advanced technologies without dealing effectively with manufacturing variability can actually put a design at a competitive disadvantage due to low parametric yield.

"Successful IC implementation requires a detailed understanding of how variability affects both functional and parametric yield. Customers need a manufacturing-aware engineering approach that extends across the entire physical implementation life cycle, starting with cell library development and extending through place and route, physical verification, layout optimization, mask preparation, testing, and failure analysis.

"They need a design flow that helps them "co-optimize" for both performance and yield simultaneously, based on accurate models of manufacturing process variability. The ability to do this quickly and effectively can give IC designers a powerful competitive advantage," Sawicki said.

There is no silver bullet! It takes a broad-based, well-integrated approach to have a significant and consistent impact on manufacturability.

According to him, Mentor Graphics provides a complete manufacturing-aware design-to-silicon solution addressing random particle effects, small-scale device and interconnect interactions, lithographic distortions and process window variations, and thickness variations resulting from chemical-mechanical polishing (CMP) and variable film deposition and etch rates.

"Our tools incorporate comprehensive, highly-accurate models that have been tuned and verified for specific manufacturing environments, and address every stage of the digital IC implementation life cycle," he added.

So, how is Mentor handling 45nm and 32nm design challenges?

Sawicki added: "Advanced process nodes present challenges at every stage of IC implementation, from place-and-route, through physical verification, layout enhancement, testing and yield analysis. Mentor has a complete design-to-silicon flow that addresses the critical challenges of IC implementation at every stage."

Magma's YieldManager could make solar 'rock'!

Make no mistake, folks! The EDA guys are getting their act together to penetrate the solar/PV segment!! Magma's YieldManager is a great example of that effort! Yes, we all know the troubles of the EDA industry as well as of the key players. However, let's not ignore this initiative from Magma!

Recently, Magma Design Automation Inc. announced the development of a new yield enhancement software system, the YieldManager software system, which is customized for solar fabs to improve conversion efficiency, increase yield and reduce the manufacturing costs of solar cells.

Magma is collaborating with Pegasus Semiconductor-Solar to refine the product specifications and test the new product, based on Magma's YieldManager.

This is an interesting development, especially from the point of view of the solar/PV industry! Even more significant is the entrance of the EDA community [the one being Synopsys] into solar/PV, a segment, which has witnessed a substantial amount of investments worldwide, and specifically, in India.

It was fun catching up with Ankush Oberai, VP, Failure Analysis Business Unit, Magma Design Automation, in Silicon Valley, to find out more about the YieldManager software system, what it can do for the solar/PV industry, and why Magma decided to venture into an 'unchartered territory'.

The first and most obvious thing, why YieldManager?

Ankush Oberoi says that in semiconductors, yield impacting parameters which are regularly monitored are mostly extrinsic, i.e., from outside, such as particles, over-exposure, under-exposure and miss-processing. In solar cells, the yield impacting parameters are mostly intrinsic, that is, something built into the solar cell material which can NOT be easily seen. Thus, a different "eye" is needed to see the solar parameters. The "eye" is the YieldManager here!!!

It would NOT be either inspection tools or litho optical proximity correction (OPC) detector. The solar cell efficiency is directly influenced by electro-physics of solar materials. A YieldManger is required to monitor any changes in those efficiency impacting parameters.

The most important parameter is the lifetime of current-generating carriers. As the solar energy generates the "hole-electron" pairs, they are collected separately as electricity.

If the solar material is "dirty" with many crystalline boundaries as in thin film solar cells, the solar generated hole-electrons get pulled into those crystalline boundaries and do not contribute to the electricity generation.

"Thus, if we can find a solar yield management system to detect the very subtle change in carrier lifetime, then we are at home with a greatest Home Run in solar cell business," he contends.

Given the EDA background, why did Magma decide on a yield management technology?

He adds that yield management technology was acquired by Magma as part of the Knights Technology acquisition in Nov 2006. Magma's Fab Business Unit (formerly, Knights Technology) is a pioneer (since 1994) in yield management for semiconductor technology.

The product is deployed and used in leading fabs around the world to help manage production wafer yield. Yield management has also been deployed for mask making and LCD productions.

It would be interesting to know how Magma's new product will allow solar fabs to better monitor all metrology, inspection and performance data throughout the manufacturing process.

Oberoi says: "For Si wafer solar cell, the most important parameter to monitor is the solar conversion efficiency impacting parameters. An example would be a carrier lifetime.

"If the carrier lifetime fluctuates more than normal, the solar Yield Manager will quickly examine all of the key data, i.e., metrology, inspection and performance data, to pinpoint out potential root-causes of the fluctuation problem."

For thin film solar cell, particles, laser cutting integrity and film thickness uniformity would be main things to monitor. Those data are quite similarly collected, as in semiconductors, and would be monitored as similar ways. The Solar Yield Manager would do well as proven in semiconductors in this case.

Next, it is important to find out how will the YieldManager enable fab operators to identify and correct root causes of solar-efficiency and yield degradation caused by subtle fab processing fluctuations or instability.

According to Oberoi, the carrier lifetime, which could be caused by various factors, is the most critical parameter to monitor for achieving and maintaining the good solar conversion efficiency.

He says: "As the Solar Yield Manager carefully monitors those factors, blindly committing ~400,000 wafers a day can be eliminated, when critical process instability starts appearing and persists. The solar conversion efficiency impacting factors could be monitored differently by different solar fabs."

Some fabs may not have capabilities to monitor those factors. The Solar Yield Manager would define those metrology and performance tool requirements, when released.

It is also interesting to learn how improving the energy conversion efficiency, reducing the manufacturing costs and increasing the yield of silicon wafer-based solar cells are critical to the growth of the solar market.

Currently, the Si wafer for solar cell costs $2~$2.5/watt due to the severe shortage of Si. The selling price of a solar cell is $3~$3.5/watt, that is, the material cost is 60~70 percent of the solar cell price.

No market or industry would prevail with the 60~70 percent material cost, adds Oberoi. Thus, every milli-watt squeezed out of a solar cell would be very critically important for proliferation of solar industry.

In order to increase the power output of a solar cell, the solar conversion efficiency must be maximized. Once maximized, sustaining the good solar efficiency is the name of the game in the solar cell manufacturing business.

The effective manufacturing cost will be drastically lowered, if bad solar cells with poor solar efficiency is minimally produced. That is, some fabs will use ~400,000 wafers a day to generate ~500 M-Watt a year, whereas some ~450,000 wafers to do the same with poorer solar efficiency.

Innovation in the solar fabrication process must be accelerated, and today, no other enterprise-wide yield enhancement software exists for solar fabs.

Oberoi says: "Solar cell is an old technology, but a very new industry, simply because not enough money was being invested. Now, money is pouring into the solar industry and products like solar Yield will start to appear. It is not known yet that anyone commercially has tried to develop a similar product."

Global estimate of solar/PV industry
There are several publications with recent estimates. The annual solar cell installation in the world: Germany ~46 percent, Japan ~23 percent, USA ~9 percent, Spain ~6 percent, Italy ~4 percent, the rest of Europe ~1 percent, the rest of Asia, including India and China ~6 percent, and the rest of world ~5 percent in 2006.

Magma is currently in the design and implementation stages of the product and plan to have version 1.0 of the product commercially available in Q1-09. The company has targeted solar fabs based in Asia that are eager for early implementation of the solar yield product.

Right then: those planning or having solar fabs! Now's the time to test that home run theory with the YieldManager.

Yield management, DFM in the Indian context

There is a lack of satisfactory match that needs to be overcome for India to go up in the semiconductor value chain. This should be overcome by training, adopting new methodologies/tools and taking care of it from the beginning in the design phase, according to S. Uma Mahesh, co-founder CEO of Indrion Technologies, in this discussion on yield management and DFM in the Indian context.

It is said that design for manufacturing (DFM) means design for money and design for profitability. What are designers doing about maintaining these? Most importantly, are the designers conscious of yield. According to Uma Mahesh, it is not as much as they should! It is still not mapped to technical parameters. That is, what if they do will effect the yield to what extent!

On DFM, essentially, it implies that design takes care of effects of manufacturing, by factoring for it in all phases of design -- beginning with architecture. This is done in terms of design margins, matching the projected performance numbers to those achieved.

This requires designers to factor for it, primarily the cross talk, electro migration, signal 'bouncing', etc., by planning for the power bus, clock bus architecture, their widths. And similarly, at the frontend level, by planning for the margins in timings, clock skews and latencies.

Teams are increasingly planning for these from different stages of front-end design and also in the physical design planning and later, by using tools that are actually aware of the DFM, SI effects, respectively.

Are designers as conscious of yield as they should be? If not, why and what should they do to improve? To this, it had more to do with 'realizing the importance of design decisions on yield'. DFY, DFM, etc., are new developments, that are of higher importance for some designs over other -- for example, for high frequency, high performance, lower geometry designs. More importance should be give to these aspects by companies when they train their engineers.

Companies should try to incorporate these aspects in training and inculcate the importance of these to the engineers, explaining the importance of these factors to the products they develop. In short, more education of the factors are required.

Is the yield accurately mapping into the technical parameters that would ultimately lead to higher tapeout percentage? What are the challenges and how can those be overcome? This was not yet happening for the reasons below.

The essential tools are in the process of becoming part of the design process and they do a good job. However, this is still an evolving space, and hence, lots of opportunity for EDA tool companies, startups, as can be noticed in the industry activity globally.