BERNIN, FRANCE: The Soitec Group (Euronext Paris), the world’s leading supplier of silicon-on-insulator (SOI) and other engineered substrates for the microelectronics industry, announced today that it has entered into collaboration with IBM to pioneer 22nm node and beyond silicon wafer substrate and bonding techniques that will enable wafer-level, three-dimensional (3D) integration technology for next-generation ICs.
The two companies have been working together for many years to improve the design and specifications of advanced silicon wafer substrates to meet the needs of IBM’s manufacturing roadmap.
The objective of this new collaboration is to develop highly flexible and cost-effective solutions for wafer-to-wafer stacking, a semiconductor technology designed to yield ICs with faster speeds and higher performance.
In joining IBM's 3D integration effort, Soitec will leverage its Smart Stacking technology and all of its wafer-level bonding expertise including oxide-to-oxide and metal-to-metal molecular bonding—developed in collaboration with CEA/Leti (the Electronics and Information Technology Laboratory of the of the French Atomic Energy Commission).
"This collaboration with Soitec is another step in IBM’s drive to accelerate 3D integration technology, and reinforces the expanding IBM ecosystem of leading companies and research organizations that are working together to achieve significant advances in semiconductor and packaging technology," said Dr. Gary Patton, Vice President, Semiconductor Research and Development Center, IBM.
"Through these collaborations, IBM intends to accelerate the development of emerging 3D integration technology and demonstrate the possibilities of achieving higher circuit densities, faster speeds and lower power usage with this vertical integration approach.”
“Soitec has continuously supported IBM’s development programs over the past 15 years with our SOI and other engineered substrates. We expect this new collaboration with IBM will help solve the challenges that IBM is addressing through its 3D program,” said Carlos Mazuré, CTO of Soitec.
Showing posts with label Soitec. Show all posts
Showing posts with label Soitec. Show all posts
Tuesday, July 14, 2009
Tuesday, June 16, 2009
Soitec's 300mm ultra-thin SOI qualified and ready
BERNIN, FRANCE: The Soitec Group (Euronext Paris), the world's leading supplier of engineered substrates for the microelectronics industry, announced that its 300mm ultra-thin SOI (UTSOI) wafer platform is qualified and ready to support fully depleted (FD) device applications scheduled on the industry's CMOS roadmaps for 22nm and beyond.
Soitec introduced its 300mm UTSOI wafer platform, fabricated using the company's patented Smart Cut(TM) technology, at SEMICON West last year, and since then has been actively working on product options, process optimization, and internal and customer qualifications.
The latest breakthrough is Soitec's ability to manufacture SOI with extremely thin top-layer silicon (20nm) to a thickness uniformity tolerance of plus or minus5 A (angstroms) in high volume with high yields. The specific parameters of the final SOI substrate can be tailored to customer applications, and manufactured with the same yields and similar costs as the current generation of mainstream SOI wafers.
FD SOI has been used commercially for many years, but mainly for niche applications. Now industry leaders are reporting the advantages of fully depleted SOI for mainstream applications.
"On fully depleted SOI, we've demonstrated 25nm high-k metal-gate devices with matching characteristics far superior to those obtained on bulk silicon," reported Dr. Olivier Faynot, Director of Advanced SOI technologies Development at CEA-Leti. "As it eliminates the need to dope the channel region, FD SOI solves threshold voltage (Vt) variability challenges at current and future nodes, while maintaining excellent Ion and Ioff characteristics and drastically reducing gate leakage current. With this uniform ultra-thin film SOI substrate, Soitec is delivering a solution for substantially improving Vt control of the CMOS device."
"UTSOI provides a solid foundation for planar and ultra-thin body devices, giving designers the ability to drastically cut power consumption and leakage while preserving performance. It simplifies the overall CMOS architecture, thus reducing the cost of ownership below a bulk approach," stated Paul Boudre, COO of the Soitec Group. "We are fully prepared to support our partners in fine tuning their manufacturing process steps to meet ultra uniformity requirements, and deliver maximum value from this ultra-thin layer advantage."
Soitec introduced its 300mm UTSOI wafer platform, fabricated using the company's patented Smart Cut(TM) technology, at SEMICON West last year, and since then has been actively working on product options, process optimization, and internal and customer qualifications.
The latest breakthrough is Soitec's ability to manufacture SOI with extremely thin top-layer silicon (20nm) to a thickness uniformity tolerance of plus or minus5 A (angstroms) in high volume with high yields. The specific parameters of the final SOI substrate can be tailored to customer applications, and manufactured with the same yields and similar costs as the current generation of mainstream SOI wafers.
FD SOI has been used commercially for many years, but mainly for niche applications. Now industry leaders are reporting the advantages of fully depleted SOI for mainstream applications.
"On fully depleted SOI, we've demonstrated 25nm high-k metal-gate devices with matching characteristics far superior to those obtained on bulk silicon," reported Dr. Olivier Faynot, Director of Advanced SOI technologies Development at CEA-Leti. "As it eliminates the need to dope the channel region, FD SOI solves threshold voltage (Vt) variability challenges at current and future nodes, while maintaining excellent Ion and Ioff characteristics and drastically reducing gate leakage current. With this uniform ultra-thin film SOI substrate, Soitec is delivering a solution for substantially improving Vt control of the CMOS device."
"UTSOI provides a solid foundation for planar and ultra-thin body devices, giving designers the ability to drastically cut power consumption and leakage while preserving performance. It simplifies the overall CMOS architecture, thus reducing the cost of ownership below a bulk approach," stated Paul Boudre, COO of the Soitec Group. "We are fully prepared to support our partners in fine tuning their manufacturing process steps to meet ultra uniformity requirements, and deliver maximum value from this ultra-thin layer advantage."
Friday, May 15, 2009
ST, Soitec to develop next-gen CMOS image sensors technology
GRENOBLE, FRANCE: STMicroelectronics and Soitec announced an exclusive joint cooperation between the two companies that will lead to the development of 300mm wafer-level backside-illumination (BSI) technology for next-generation image sensors in consumer products.
The resolution of today’s leading-edge image sensors is continuously increasing, while demand is high for the overall reduction of the camera-module footprint, particularly in consumer markets. This means the necessary development of smaller individual pixel sizes, while maintaining pixel sensitivity to produce high-quality images. Backside illumination is a key enabling technology to meet this challenge in the development of next-generation image sensors.
The agreement between the two companies includes the licensing by Soitec to ST of the Smart Stacking™ bonding technology for the manufacturing of backside-illumination sensors on 300mm wafers. This technology, developed by Soitec’s Tracit business unit, leverages molecular bonding, and mechanical, as well as chemical thinning. ST will develop a new generation of image sensors based on its advanced derivative-CMOS process technology at 65nm and beyond, at its 300mm facility in Crolles, France. In combination with ST’s advanced wafer-level manufacturing capabilities, the Smart Stacking technology will enable ST to increase its leadership in developing and supplying high-performance image sensors for mobile consumer products.
“Backside illumination technology is a key ingredient in the small-pixel, high-image-quality race for the development of leading-edge image sensors,” said Eric Aussedat, Group Vice President and General Manager, Imaging Division, STMicroelectronics. “Partnering with Soitec will help quickly deploy the Smart Stacking technology into ST’s camera products. This agreement will accelerate the development of advanced and superior cost-competitive image-sensor processes, and further confirms the Grenoble region as a world-class center of expertise for advanced CMOS imaging technologies.”
“We are very pleased that STMicroelectronics has chosen our Smart Stacking technology for their BSI product,” said André-Jacques Auberton-Hervé, chairman and president of the Soitec Group. “This technology developed by our Tracit business unit, supports fast implementation of advanced processes involving substrate engineering and 3D integration. We are glad to support ST’s commitment to innovation for the benefit of their customers.”
The resolution of today’s leading-edge image sensors is continuously increasing, while demand is high for the overall reduction of the camera-module footprint, particularly in consumer markets. This means the necessary development of smaller individual pixel sizes, while maintaining pixel sensitivity to produce high-quality images. Backside illumination is a key enabling technology to meet this challenge in the development of next-generation image sensors.
The agreement between the two companies includes the licensing by Soitec to ST of the Smart Stacking™ bonding technology for the manufacturing of backside-illumination sensors on 300mm wafers. This technology, developed by Soitec’s Tracit business unit, leverages molecular bonding, and mechanical, as well as chemical thinning. ST will develop a new generation of image sensors based on its advanced derivative-CMOS process technology at 65nm and beyond, at its 300mm facility in Crolles, France. In combination with ST’s advanced wafer-level manufacturing capabilities, the Smart Stacking technology will enable ST to increase its leadership in developing and supplying high-performance image sensors for mobile consumer products.
“Backside illumination technology is a key ingredient in the small-pixel, high-image-quality race for the development of leading-edge image sensors,” said Eric Aussedat, Group Vice President and General Manager, Imaging Division, STMicroelectronics. “Partnering with Soitec will help quickly deploy the Smart Stacking technology into ST’s camera products. This agreement will accelerate the development of advanced and superior cost-competitive image-sensor processes, and further confirms the Grenoble region as a world-class center of expertise for advanced CMOS imaging technologies.”
“We are very pleased that STMicroelectronics has chosen our Smart Stacking technology for their BSI product,” said André-Jacques Auberton-Hervé, chairman and president of the Soitec Group. “This technology developed by our Tracit business unit, supports fast implementation of advanced processes involving substrate engineering and 3D integration. We are glad to support ST’s commitment to innovation for the benefit of their customers.”
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