SEOUL, SOUTH KOREA: Hynix Semiconductor Inc. announced the appointment of Ji Bum Kim as the new Chief Marketing Officer. J.B. Kim replaces Dae Su Kim, who has currently resigned.
In his new position, J.B. Kim will be responsible for all Sales and Marketing functions at Hynix, covering DRAM, NAND Flash, and CMOS Image Sensors.
J.B. Kim has spent 25 years in the semiconductor industry holding management positions in both engineering and marketing. His most recent position was Senior VP of Technical Marketing and Product Planning at Hynix where he has worked since 1999. Prior to this, Kim was VP of Technical Marketing at Hynix Semiconductor America, a position he held for four years.
He started his career at LG Semicon, gaining rich experience in semiconductor memory design, process and device engineering, for a period spanning 16 years. LG Semicon merged with Hyundai Electronics in 1999, resulting in the creation of Hynix.
“We are pleased to appoint J.B. Kim as the new CMO. Kim will bring valuable engineering and marketing experience to Hynix with his knowledge of the emerging technologies and applications. He will greatly help Hynix develop new products, enter new markets and expand our customer base,” said Dr Jong Kap Kim, CEO of Hynix.
Showing posts with label CMOS image sensors. Show all posts
Showing posts with label CMOS image sensors. Show all posts
Tuesday, August 4, 2009
Wednesday, June 10, 2009
Cypress designs BSI digital output CMOS image sensor for NEC TOSHIBA
SAN JOSE, USA: Cypress Semiconductor Corp. (NYSE: CY) today announced it has designed a custom back-side illuminated CMOS image sensor for a satellite hyperspectral imaging application from NEC TOSHIBA Space Systems Ltd.
Back-side illumination (BSI) increases the amount of light and the spectral range that can be captured by each pixel, delivering ultra-high-sensitivity images. The custom sensor is the industry’s first to combine a radiation-tolerant BSI architecture with a high-speed digital output interface, enabling detailed analysis from space of hyperspectral images that capture information from across the electromagnetic spectrum.
Cypress and NEC TOSHIBA Space Systems expect the design to be in space-qualified flight models by mid-2010. The sensor is expected to be available for other space and military applications after flight qualification is completed.
BSI allowed Cypress to use noise reduction techniques such as correlated double sampling without compromising spectral response or sensitivity. In addition to the BSI architecture, the imager integrates Cypress’s patented global-shutter technology, which enables fast frame rates with the ability to read one frame while the next is being captured.
Cypress’s global shuttering is used in a wide range of products, including the world’s fastest CMOS image sensors. The sensor is arranged in a 1024 column x 256 row configuration. The design includes on-board analog-to-digital converters and a high-speed digital interface tailored for space applications.
Cypress will be demonstrating its industry-leading custom and standard CMOS image sensor solutions at the 2009 Image Sensing Show in Yokohama, Japan from June 10-12, 2009 in Booth #69.
“We selected Cypress for this project based on their extensive experience in designing and back-side illuminated products and radiation-tolerant CMOS sensors for space, as well as for their leading global shuttering technology,” said the Program Manager at NEC TOSHIBA Space Systems. “The imager’s ability to deliver highly detailed images at fast speeds is applicable to many applications beyond space.”
“This sensor represents a significant advance in spectral response and sensitivity for CMOS-based space applications using back-side illumination technology,” said Cliff Drowley, vice president of Cypress’s image sensor business unit. “Cypress worked closely with NEC TOSHIBA Space Systems to develop this unique architecture, and we look forward to expanding its reach to new applications.”
Back-side illumination (BSI) increases the amount of light and the spectral range that can be captured by each pixel, delivering ultra-high-sensitivity images. The custom sensor is the industry’s first to combine a radiation-tolerant BSI architecture with a high-speed digital output interface, enabling detailed analysis from space of hyperspectral images that capture information from across the electromagnetic spectrum.
Cypress and NEC TOSHIBA Space Systems expect the design to be in space-qualified flight models by mid-2010. The sensor is expected to be available for other space and military applications after flight qualification is completed.
BSI allowed Cypress to use noise reduction techniques such as correlated double sampling without compromising spectral response or sensitivity. In addition to the BSI architecture, the imager integrates Cypress’s patented global-shutter technology, which enables fast frame rates with the ability to read one frame while the next is being captured.
Cypress’s global shuttering is used in a wide range of products, including the world’s fastest CMOS image sensors. The sensor is arranged in a 1024 column x 256 row configuration. The design includes on-board analog-to-digital converters and a high-speed digital interface tailored for space applications.
Cypress will be demonstrating its industry-leading custom and standard CMOS image sensor solutions at the 2009 Image Sensing Show in Yokohama, Japan from June 10-12, 2009 in Booth #69.
“We selected Cypress for this project based on their extensive experience in designing and back-side illuminated products and radiation-tolerant CMOS sensors for space, as well as for their leading global shuttering technology,” said the Program Manager at NEC TOSHIBA Space Systems. “The imager’s ability to deliver highly detailed images at fast speeds is applicable to many applications beyond space.”
“This sensor represents a significant advance in spectral response and sensitivity for CMOS-based space applications using back-side illumination technology,” said Cliff Drowley, vice president of Cypress’s image sensor business unit. “Cypress worked closely with NEC TOSHIBA Space Systems to develop this unique architecture, and we look forward to expanding its reach to new applications.”
Friday, May 15, 2009
ST, Soitec to develop next-gen CMOS image sensors technology
GRENOBLE, FRANCE: STMicroelectronics and Soitec announced an exclusive joint cooperation between the two companies that will lead to the development of 300mm wafer-level backside-illumination (BSI) technology for next-generation image sensors in consumer products.
The resolution of today’s leading-edge image sensors is continuously increasing, while demand is high for the overall reduction of the camera-module footprint, particularly in consumer markets. This means the necessary development of smaller individual pixel sizes, while maintaining pixel sensitivity to produce high-quality images. Backside illumination is a key enabling technology to meet this challenge in the development of next-generation image sensors.
The agreement between the two companies includes the licensing by Soitec to ST of the Smart Stacking™ bonding technology for the manufacturing of backside-illumination sensors on 300mm wafers. This technology, developed by Soitec’s Tracit business unit, leverages molecular bonding, and mechanical, as well as chemical thinning. ST will develop a new generation of image sensors based on its advanced derivative-CMOS process technology at 65nm and beyond, at its 300mm facility in Crolles, France. In combination with ST’s advanced wafer-level manufacturing capabilities, the Smart Stacking technology will enable ST to increase its leadership in developing and supplying high-performance image sensors for mobile consumer products.
“Backside illumination technology is a key ingredient in the small-pixel, high-image-quality race for the development of leading-edge image sensors,” said Eric Aussedat, Group Vice President and General Manager, Imaging Division, STMicroelectronics. “Partnering with Soitec will help quickly deploy the Smart Stacking technology into ST’s camera products. This agreement will accelerate the development of advanced and superior cost-competitive image-sensor processes, and further confirms the Grenoble region as a world-class center of expertise for advanced CMOS imaging technologies.”
“We are very pleased that STMicroelectronics has chosen our Smart Stacking technology for their BSI product,” said André-Jacques Auberton-Hervé, chairman and president of the Soitec Group. “This technology developed by our Tracit business unit, supports fast implementation of advanced processes involving substrate engineering and 3D integration. We are glad to support ST’s commitment to innovation for the benefit of their customers.”
The resolution of today’s leading-edge image sensors is continuously increasing, while demand is high for the overall reduction of the camera-module footprint, particularly in consumer markets. This means the necessary development of smaller individual pixel sizes, while maintaining pixel sensitivity to produce high-quality images. Backside illumination is a key enabling technology to meet this challenge in the development of next-generation image sensors.
The agreement between the two companies includes the licensing by Soitec to ST of the Smart Stacking™ bonding technology for the manufacturing of backside-illumination sensors on 300mm wafers. This technology, developed by Soitec’s Tracit business unit, leverages molecular bonding, and mechanical, as well as chemical thinning. ST will develop a new generation of image sensors based on its advanced derivative-CMOS process technology at 65nm and beyond, at its 300mm facility in Crolles, France. In combination with ST’s advanced wafer-level manufacturing capabilities, the Smart Stacking technology will enable ST to increase its leadership in developing and supplying high-performance image sensors for mobile consumer products.
“Backside illumination technology is a key ingredient in the small-pixel, high-image-quality race for the development of leading-edge image sensors,” said Eric Aussedat, Group Vice President and General Manager, Imaging Division, STMicroelectronics. “Partnering with Soitec will help quickly deploy the Smart Stacking technology into ST’s camera products. This agreement will accelerate the development of advanced and superior cost-competitive image-sensor processes, and further confirms the Grenoble region as a world-class center of expertise for advanced CMOS imaging technologies.”
“We are very pleased that STMicroelectronics has chosen our Smart Stacking technology for their BSI product,” said André-Jacques Auberton-Hervé, chairman and president of the Soitec Group. “This technology developed by our Tracit business unit, supports fast implementation of advanced processes involving substrate engineering and 3D integration. We are glad to support ST’s commitment to innovation for the benefit of their customers.”
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