SOI makes electronics simply greener

BOSTON, USA: The SOI Industry Consortium recently launched SOI Simply Greener, an initiative encouraging broader application of the energy saving benefits of silicon-on-insulator (SOI) technology by the electronics industry.

Semiconductor chips manufactured on SOI instead of traditional bulk silicon can realize energy savings of 30 percent or more when designed with the same feature size at equivalent performance. Broader adoption and usage of SOI technology by the electronics industry are consistent with global initiatives to both lower global electric power demand and reduce electric power bills for businesses and consumers.

“SOI is simply greener -– and this story needs to be told,” said Horacio Mendez, Executive Director of the SOI Industry Consortium. “The first high-volume SOI applications were geared to high performance, but even there, the power-saving benefits are now apparent.

The fact that 18 of the top 20 most power-efficient supercomputers [source: www.green500.org] are built with SOI demonstrates SOI’s ‘GreenIT’ benefits for enterprise applications. Also, current versions of the top three consumer game consoles each include SOI-based chips, but much more can be done to help consumers lower their power bills through broader SOI usage. The SOI Consortium’s ‘green’ campaign will drive that point home to the design community.”

The energy-efficiency advantage of SOI technology contributes to both increased performance and reduced power consumption – the magnitude of benefit applied to each is the designer’s choice. Since “apples-to-apples” comparisons are impractical for most design teams to make, results from two studies are offered by consortium members to demonstrate this point.

• A benchmark analysis was performed by ARM Holdings using a 24-stage interconnect-loaded datapath circuit. When comparing IBM’s 45nm bulk silicon high performance and 45nm SOI technologies, the SOI implementation resulted in a 25 percent circuit area reduction, 66 percent reduction in static power leakage and nearly 22 percent reduction in dynamic power with 5% higher performance.
• A consumer product chip design that was migrated from 65nm bulk silicon high performance to IBM’s 45nm SOI technology realized a 50 percent increase in operating frequency, more than 64% reduction in die area and a 38 percent reduction in power consumption.

Whether designers put the emphasis on increasing or maintaining performance, significant power savings (as well as area savings) were realized with a move to SOI.

“As we detailed in our recent report Semiconductor Technologies: The Potential to Revolutionize US Energy Productivity, semiconductors already are the leading factor behind energy efficiency gains,” said lead author of the report John A. “Skip” Laitner, Director, Economic and Social Analysis, American Council for an Energy-Efficient Economy (ACEEE).

“SOI offers a major advance in the power efficiency of electronics, and with appropriate public policy, investment and usage these semiconductor technology gains can contribute to cumulative net electricity bill savings of $800 billion through 2030 for consumers and businesses in the United States alone, as well as creating an average of 500,000 new jobs per year and reducing energy-related CO2 emissions by more than 400 million metric tons annually over the period 2010 through 2030.”

In a survey jointly conducted last year by the Global Semiconductor Alliance and the SOI Industry Consortium, semiconductor designers indicated overwhelmingly that power savings is their primary driver for considering an SOI-based solution.

To meet this market demand, the 28 member companies, research and academic institutions of the SOI Industry Consortium are stepping up collaboration in the areas of new process development, chip design techniques, designer training, electronic design automation (EDA) productivity tools, and intellectual property (IP) development to provide broader access to SOI technology and ecosystem support for designers, and to enable the electronics industry, its customers and the global community to fully realize the power-saving advantages of this greener technology.

The SOI Industry Consortium welcomes companies, organizations, government and academic institutions to join the group in applying the full benefits of SOI-based electronics to global sustainability challenges and lowering the total cost-of-ownership of electronics.

Soitec, IBM to develop wafer-level 3D integration technology

BERNIN, FRANCE: The Soitec Group (Euronext Paris), the world’s leading supplier of silicon-on-insulator (SOI) and other engineered substrates for the microelectronics industry, announced today that it has entered into collaboration with IBM to pioneer 22nm node and beyond silicon wafer substrate and bonding techniques that will enable wafer-level, three-dimensional (3D) integration technology for next-generation ICs.

The two companies have been working together for many years to improve the design and specifications of advanced silicon wafer substrates to meet the needs of IBM’s manufacturing roadmap.

The objective of this new collaboration is to develop highly flexible and cost-effective solutions for wafer-to-wafer stacking, a semiconductor technology designed to yield ICs with faster speeds and higher performance.

In joining IBM's 3D integration effort, Soitec will leverage its Smart Stacking technology and all of its wafer-level bonding expertise including oxide-to-oxide and metal-to-metal molecular bonding—developed in collaboration with CEA/Leti (the Electronics and Information Technology Laboratory of the of the French Atomic Energy Commission).

"This collaboration with Soitec is another step in IBM’s drive to accelerate 3D integration technology, and reinforces the expanding IBM ecosystem of leading companies and research organizations that are working together to achieve significant advances in semiconductor and packaging technology," said Dr. Gary Patton, Vice President, Semiconductor Research and Development Center, IBM.

"Through these collaborations, IBM intends to accelerate the development of emerging 3D integration technology and demonstrate the possibilities of achieving higher circuit densities, faster speeds and lower power usage with this vertical integration approach.”

“Soitec has continuously supported IBM’s development programs over the past 15 years with our SOI and other engineered substrates. We expect this new collaboration with IBM will help solve the challenges that IBM is addressing through its 3D program,” said Carlos Mazuré, CTO of Soitec.