SOI makes electronics simply greener

BOSTON, USA: The SOI Industry Consortium recently launched SOI Simply Greener, an initiative encouraging broader application of the energy saving benefits of silicon-on-insulator (SOI) technology by the electronics industry.

Semiconductor chips manufactured on SOI instead of traditional bulk silicon can realize energy savings of 30 percent or more when designed with the same feature size at equivalent performance. Broader adoption and usage of SOI technology by the electronics industry are consistent with global initiatives to both lower global electric power demand and reduce electric power bills for businesses and consumers.

“SOI is simply greener -– and this story needs to be told,” said Horacio Mendez, Executive Director of the SOI Industry Consortium. “The first high-volume SOI applications were geared to high performance, but even there, the power-saving benefits are now apparent.

The fact that 18 of the top 20 most power-efficient supercomputers [source: www.green500.org] are built with SOI demonstrates SOI’s ‘GreenIT’ benefits for enterprise applications. Also, current versions of the top three consumer game consoles each include SOI-based chips, but much more can be done to help consumers lower their power bills through broader SOI usage. The SOI Consortium’s ‘green’ campaign will drive that point home to the design community.”

The energy-efficiency advantage of SOI technology contributes to both increased performance and reduced power consumption – the magnitude of benefit applied to each is the designer’s choice. Since “apples-to-apples” comparisons are impractical for most design teams to make, results from two studies are offered by consortium members to demonstrate this point.

• A benchmark analysis was performed by ARM Holdings using a 24-stage interconnect-loaded datapath circuit. When comparing IBM’s 45nm bulk silicon high performance and 45nm SOI technologies, the SOI implementation resulted in a 25 percent circuit area reduction, 66 percent reduction in static power leakage and nearly 22 percent reduction in dynamic power with 5% higher performance.
• A consumer product chip design that was migrated from 65nm bulk silicon high performance to IBM’s 45nm SOI technology realized a 50 percent increase in operating frequency, more than 64% reduction in die area and a 38 percent reduction in power consumption.

Whether designers put the emphasis on increasing or maintaining performance, significant power savings (as well as area savings) were realized with a move to SOI.

“As we detailed in our recent report Semiconductor Technologies: The Potential to Revolutionize US Energy Productivity, semiconductors already are the leading factor behind energy efficiency gains,” said lead author of the report John A. “Skip” Laitner, Director, Economic and Social Analysis, American Council for an Energy-Efficient Economy (ACEEE).

“SOI offers a major advance in the power efficiency of electronics, and with appropriate public policy, investment and usage these semiconductor technology gains can contribute to cumulative net electricity bill savings of $800 billion through 2030 for consumers and businesses in the United States alone, as well as creating an average of 500,000 new jobs per year and reducing energy-related CO2 emissions by more than 400 million metric tons annually over the period 2010 through 2030.”

In a survey jointly conducted last year by the Global Semiconductor Alliance and the SOI Industry Consortium, semiconductor designers indicated overwhelmingly that power savings is their primary driver for considering an SOI-based solution.

To meet this market demand, the 28 member companies, research and academic institutions of the SOI Industry Consortium are stepping up collaboration in the areas of new process development, chip design techniques, designer training, electronic design automation (EDA) productivity tools, and intellectual property (IP) development to provide broader access to SOI technology and ecosystem support for designers, and to enable the electronics industry, its customers and the global community to fully realize the power-saving advantages of this greener technology.

The SOI Industry Consortium welcomes companies, organizations, government and academic institutions to join the group in applying the full benefits of SOI-based electronics to global sustainability challenges and lowering the total cost-of-ownership of electronics.

Soitec, IBM to develop wafer-level 3D integration technology

BERNIN, FRANCE: The Soitec Group (Euronext Paris), the world’s leading supplier of silicon-on-insulator (SOI) and other engineered substrates for the microelectronics industry, announced today that it has entered into collaboration with IBM to pioneer 22nm node and beyond silicon wafer substrate and bonding techniques that will enable wafer-level, three-dimensional (3D) integration technology for next-generation ICs.

The two companies have been working together for many years to improve the design and specifications of advanced silicon wafer substrates to meet the needs of IBM’s manufacturing roadmap.

The objective of this new collaboration is to develop highly flexible and cost-effective solutions for wafer-to-wafer stacking, a semiconductor technology designed to yield ICs with faster speeds and higher performance.

In joining IBM's 3D integration effort, Soitec will leverage its Smart Stacking technology and all of its wafer-level bonding expertise including oxide-to-oxide and metal-to-metal molecular bonding—developed in collaboration with CEA/Leti (the Electronics and Information Technology Laboratory of the of the French Atomic Energy Commission).

"This collaboration with Soitec is another step in IBM’s drive to accelerate 3D integration technology, and reinforces the expanding IBM ecosystem of leading companies and research organizations that are working together to achieve significant advances in semiconductor and packaging technology," said Dr. Gary Patton, Vice President, Semiconductor Research and Development Center, IBM.

"Through these collaborations, IBM intends to accelerate the development of emerging 3D integration technology and demonstrate the possibilities of achieving higher circuit densities, faster speeds and lower power usage with this vertical integration approach.”

“Soitec has continuously supported IBM’s development programs over the past 15 years with our SOI and other engineered substrates. We expect this new collaboration with IBM will help solve the challenges that IBM is addressing through its 3D program,” said Carlos Mazuré, CTO of Soitec.

Clare's eight-channel high voltage analog switch IC

BEVERLY, USA: Clare Inc., a wholly owned subsidiary of IXYS Corp. has announced the immediate availability of the CPC7232, an eight-channel high voltage analog switch IC.

Designed using Clare’s proprietary high voltage BCDMOS on SOI (silicon on insulator) process, the CPC7232 combines high voltage, bilateral DMOS switches with low power CMOS logic. This results in the efficient control of high voltage analog signals with low voltage logic control signals. The CPC7232 is ideal for medical ultrasound imaging, test equipment, printers, and industrial measurement applications.

The CPC7232 features very low quiescent power dissipation (typically much less than 1 micro-Amp). Each of the eight high voltage, low charge injection, bi-directional outputs is capable of operating from various combinations of split power supplies up to 200V (ex. +160V/-40V, +100V/-100V, and +185V/-15V).

The high voltage outputs are controlled by data clocked into an internal 8-bit shift register and stored in an 8-bit transparent latch. The latch is controlled with enable and clear inputs. The CPC7232 integrates 35K ohm bleed resistors to discharge the capacitive loads of piezoelectric transducers, thus saving cost and PCB space.

The CPC7232 is fully specified over the 0 degree Centigrade to +70 degrees Centigrade commercial temperature range, and is available in industry standard 48-lead LQFP (CPC7232K) and 28-lead PLCC (CPC7232W) packages.

An assessment of 3D IC technology

DUBLIN, IRELAND: Research and Markets has announced the addition of Frost & Sullivan's new report "3D IC Technology - An Assessment" to its offering.

This Frost & Sullivan research service titled 3D IC Technology - An Assessment, provides an insight into the technology development scenario of three-dimensional integrated circuit (3D IC) technologies.

This research service also provides a detailed review of the key developmental efforts around the globe, funding scenario, patent analysis, and insights into the key growth patterns that mark the evolution of 3D IC technologies in the industrial space. In this research, Frost & Sullivan's expert analysts thoroughly examine the following technologies: 3D IC, 3D packaging, system in package, and silicon on insulator (SOI) technologies.

'Z' dimension of semiconductor growth impacts advances in image sensor and memory market
There are several development initiatives involving form factor of IC technology, with the much spoken-about difficulty of progressing along the Moore's curve. 3D IC technology assures higher levels of miniaturization and integration, focuses on portraying advances in interconnect technologies, and a reduction of interconnect delays.

3D IC technologies guarantee a significant increase in functionality and performance of components by a heterogeneous integration of materials, devices, and signals. "The adoption of 3D ICs integration technology in different applications is likely to be driven by its capability to reduce process cost, enhance interconnect density, and offer smaller form factors," notes the analyst of this research.

"Although through silicon vias (TSV) has categorically evolved to be a highly competent solution for performance when gauged with conventional interconnect technologies, the industry is still in the process of establishing it as a commercially viable solution for dominant penetration in diverse application sectors."

Currently, the industry is in a position to leverage the capabilities of 3D IC solutions in the image sensors market. Memory stacking is next in line with image sensors in terms of adoption of 3D IC technologies.

At the bottom rung, 3D IC solutions will find opportunities in applications that involve homogeneous integration, while scientists are working toward a technology for applications that need heterogeneous integration of wafers.

As the entire 3D IC technology is focusing on wafer stacking, development efforts around the globe are striving to resolve challenges associated with the silicon on insulator (SOI) domain. The industry is also determined to establish an appropriate performance guideline to enable it to choose between the 'via first' and the 'via last' approaches.

The ability to handle thin wafer, proper bonding technologies for heterogeneous bonding, along with reducing the costs associated with the TSV process are some other critical issues that need to be addressed. "Despite widespread industrial efforts in the 3D IC domain, fundamental technology challenges continue to exist," notes the analyst. "However, the technology space is collaboratively striving to resolve them."

The need of the hour is to establish clear performance metrics for all the evolving processes. For instance, in the case of TSV, the industry has explored aspects, such as the cost of operation (COO) of the process, but lacks a proper standard to gauge the performance of a specific process established by a development group.

This will help participants know the real capabilities of their offering on a global platform. "The next decade of 3D IC evolution will significantly rely on the industry's capability to develop a performance standard for the various segments of 3D IC domain, that are currently being explored," concludes the analyst.