BEAVERTON, USA: BeSang Inc., a fabless semiconductor company, has successfully developed a multi-layer stacked three-dimensional (3D) integrated circuit (IC) technology.
This 3D IC technology enables ultra low-cost solid-state drives (SSD), semiconductor memories, image sensors, and high-performance logic products with large embedded memory blocks.
This 3D IC technology includes four single-crystalline silicon layers having 200nm to 60nm feature size vertical device structures which are uniquely processed at low temperatures, below 400 degree Celsius. The four single-crystalline silicon layers are formed above a silicon substrate with a metal interconnection region between them.
"Our main effort is to develop multi-layer 3D ICs which provide ultra low cost solutions to the semiconductor and microelectronics industries," said Dr. Sang-Yun Lee, CEO of BeSang.
"With this 3D IC technology, a high-definition movie can be stored on a small 3D IC chip having a terabyte storage capacity for a few dollars. High-performance cell phones with multi-functional and super fast 3D IC chips using this technology will be possible in the near future. These cell phones will be able to compete with laptops."
Unlike conventional 3D packaging technologies and 3D TSV (Through Silicon Via) technologies, where memory control logic circuits are stacked in 3D along with memory arrays, BeSang's 3D IC technology combines the control logic on the bottom substrate with the 3D memory arrays. This 3D scheme allows heat to be dissipated much more efficiently.
"One of the unique features of BeSang's 3D ICs is that heat dissipation is of less concern," said Dr. Choonsik Oh, former executive vice president and head of R&D at Hynix Semiconductor.
"Heat dissipation from logic circuitry in 3D planes must be carefully considered in the design of conventional 3D packaging and 3D TSV products. Implementing logic circuitry on the bottom substrate and memory arrays in the 3D plane is a unique feature of BeSang's 3D ICs. In this case, heat from the logic circuits flows to the bottom silicon substrate with its low thermal resistance. Because memory arrays do not operate as fast as logic, heat dissipation from the memory array is generally not a significant concern."
BeSang's multi-layer 3D ICs can be used for various applications, including high performance single chip mobile phones and ultra low cost SSD. For single chip mobile phone applications, the mobile high density flash memory and DRAM are formed in a multi-layer 3D IC on top of a baseband processor chip. This configuration provides lower power consumption, higher speed, and a smaller form factor.
SSD has been considered as a replacement for HDD. However, the high cost of SSDs has prevented their introduction into the market. BeSang's multi-layer 3D ICs provide a high-density vertical flash memory cell structure that is ideal for ultra low-cost SSDs and will accelerate the introduction of SSDs into the market.
"Combining multi-layer 3D IC and multi-bit vertical cell technologies, our plan is to implement 0.1F2 effective flash memory cell size for SSDs, which is about 20 times smaller than the cell size of conventional multi-level NAND flash," said Junil Park, vice president of process technology at BeSang.
"I believe BeSang's 3D IC has numerous advantages over emerging memories, such as resistive RAM, in terms of material reliability (i.e. silicon vs. emerging material), process complexity such as the number of mask steps per bit, and manufacturing cost."
Semiconductor manufacturing is focused on ways to miniaturize devices. However, it is very difficult for semiconductor manufacturing companies to make a respectable return on investment when high chip manufacturing costs makes it economically unfeasible to do volume production of smaller devices. Hence, BeSang's 3D IC technology, which allows more transistors to be packed into a single chip, is a crucial solution for semiconductor manufacturing.
"BeSang's single-chip 3D ICs with multi-layer stacking are a sure road to the continued miniaturization of microelectronics," said Dr. Sang-Yun Lee.
BeSang's 3D IC technology aims to provide an innovative, simpler, and more cost-effective way to enhance large functional blocks, such as memory arrays or photodiodes for image sensors, systems-on-a-chip, microprocessors, and memory control logic circuitry in advanced semiconductor chips.
Showing posts with label 3D IC technology. Show all posts
Showing posts with label 3D IC technology. Show all posts
Wednesday, August 5, 2009
Thursday, July 2, 2009
An assessment of 3D IC technology
DUBLIN, IRELAND: Research and Markets has announced the addition of Frost & Sullivan's new report "3D IC Technology - An Assessment" to its offering.
This Frost & Sullivan research service titled 3D IC Technology - An Assessment, provides an insight into the technology development scenario of three-dimensional integrated circuit (3D IC) technologies.
This research service also provides a detailed review of the key developmental efforts around the globe, funding scenario, patent analysis, and insights into the key growth patterns that mark the evolution of 3D IC technologies in the industrial space. In this research, Frost & Sullivan's expert analysts thoroughly examine the following technologies: 3D IC, 3D packaging, system in package, and silicon on insulator (SOI) technologies.
'Z' dimension of semiconductor growth impacts advances in image sensor and memory market
There are several development initiatives involving form factor of IC technology, with the much spoken-about difficulty of progressing along the Moore's curve. 3D IC technology assures higher levels of miniaturization and integration, focuses on portraying advances in interconnect technologies, and a reduction of interconnect delays.
3D IC technologies guarantee a significant increase in functionality and performance of components by a heterogeneous integration of materials, devices, and signals. "The adoption of 3D ICs integration technology in different applications is likely to be driven by its capability to reduce process cost, enhance interconnect density, and offer smaller form factors," notes the analyst of this research.
"Although through silicon vias (TSV) has categorically evolved to be a highly competent solution for performance when gauged with conventional interconnect technologies, the industry is still in the process of establishing it as a commercially viable solution for dominant penetration in diverse application sectors."
Currently, the industry is in a position to leverage the capabilities of 3D IC solutions in the image sensors market. Memory stacking is next in line with image sensors in terms of adoption of 3D IC technologies.
At the bottom rung, 3D IC solutions will find opportunities in applications that involve homogeneous integration, while scientists are working toward a technology for applications that need heterogeneous integration of wafers.
As the entire 3D IC technology is focusing on wafer stacking, development efforts around the globe are striving to resolve challenges associated with the silicon on insulator (SOI) domain. The industry is also determined to establish an appropriate performance guideline to enable it to choose between the 'via first' and the 'via last' approaches.
The ability to handle thin wafer, proper bonding technologies for heterogeneous bonding, along with reducing the costs associated with the TSV process are some other critical issues that need to be addressed. "Despite widespread industrial efforts in the 3D IC domain, fundamental technology challenges continue to exist," notes the analyst. "However, the technology space is collaboratively striving to resolve them."
The need of the hour is to establish clear performance metrics for all the evolving processes. For instance, in the case of TSV, the industry has explored aspects, such as the cost of operation (COO) of the process, but lacks a proper standard to gauge the performance of a specific process established by a development group.
This will help participants know the real capabilities of their offering on a global platform. "The next decade of 3D IC evolution will significantly rely on the industry's capability to develop a performance standard for the various segments of 3D IC domain, that are currently being explored," concludes the analyst.
This Frost & Sullivan research service titled 3D IC Technology - An Assessment, provides an insight into the technology development scenario of three-dimensional integrated circuit (3D IC) technologies.
This research service also provides a detailed review of the key developmental efforts around the globe, funding scenario, patent analysis, and insights into the key growth patterns that mark the evolution of 3D IC technologies in the industrial space. In this research, Frost & Sullivan's expert analysts thoroughly examine the following technologies: 3D IC, 3D packaging, system in package, and silicon on insulator (SOI) technologies.
'Z' dimension of semiconductor growth impacts advances in image sensor and memory market
There are several development initiatives involving form factor of IC technology, with the much spoken-about difficulty of progressing along the Moore's curve. 3D IC technology assures higher levels of miniaturization and integration, focuses on portraying advances in interconnect technologies, and a reduction of interconnect delays.
3D IC technologies guarantee a significant increase in functionality and performance of components by a heterogeneous integration of materials, devices, and signals. "The adoption of 3D ICs integration technology in different applications is likely to be driven by its capability to reduce process cost, enhance interconnect density, and offer smaller form factors," notes the analyst of this research.
"Although through silicon vias (TSV) has categorically evolved to be a highly competent solution for performance when gauged with conventional interconnect technologies, the industry is still in the process of establishing it as a commercially viable solution for dominant penetration in diverse application sectors."
Currently, the industry is in a position to leverage the capabilities of 3D IC solutions in the image sensors market. Memory stacking is next in line with image sensors in terms of adoption of 3D IC technologies.
At the bottom rung, 3D IC solutions will find opportunities in applications that involve homogeneous integration, while scientists are working toward a technology for applications that need heterogeneous integration of wafers.
As the entire 3D IC technology is focusing on wafer stacking, development efforts around the globe are striving to resolve challenges associated with the silicon on insulator (SOI) domain. The industry is also determined to establish an appropriate performance guideline to enable it to choose between the 'via first' and the 'via last' approaches.
The ability to handle thin wafer, proper bonding technologies for heterogeneous bonding, along with reducing the costs associated with the TSV process are some other critical issues that need to be addressed. "Despite widespread industrial efforts in the 3D IC domain, fundamental technology challenges continue to exist," notes the analyst. "However, the technology space is collaboratively striving to resolve them."
The need of the hour is to establish clear performance metrics for all the evolving processes. For instance, in the case of TSV, the industry has explored aspects, such as the cost of operation (COO) of the process, but lacks a proper standard to gauge the performance of a specific process established by a development group.
This will help participants know the real capabilities of their offering on a global platform. "The next decade of 3D IC evolution will significantly rely on the industry's capability to develop a performance standard for the various segments of 3D IC domain, that are currently being explored," concludes the analyst.
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