TAIWAN: Intel, Samsung, and Toshiba are reported to form a consortium and team up for developing technologies that could reduce semiconductor line widths to nearly 10 nanometers by 2016, according to an October 28, 2010 report by Nikkei.
It is reported that the three companies plan to invite roughly 10 firms in related semiconductor field to join the consortium. It is estimated that 10 billion Yens (US$123.9 million; US$1=80.7 Yens) are needed as initial funds for technologies R&D.
Half of the initial funds are projected to come from Japan's Ministry of Economy, Trade and Industry, and the other half of the funds are said to be provided by the members of the consortium.
It is reported that Samsung and Toshiba are likely to use the technologies to produce 10 nanometer-class NAND flash memory and other types of chips; while Intel are likely to use the technologies to develop microprocessors with higher speed.
Source: Asia Express, Market Intelligence & Consulting Institute (MIC), Taiwan.
Monday, November 1, 2010
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