Lattice announces Serial RapidIO 2.1 AMC evaluation platform

HILLSBORO, USA: Lattice Semiconductor Corp. announced the availability of a fully integrated evaluation and demonstration platform supporting its Serial RapidIO 2.1 endpoint core utilizing the award winning LatticeECP3 FPGA family.

The platform, including the hardware and demonstration software, is based on the industry standard Advanced Mezzanine Card (AMC) form factor and offers users the ability to investigate the lowest cost, lowest power programmable Serial RapidIO solution in the industry supporting 1x, 4x and the new 2x lane configurations at data rates up to 3.125Gbps.

The LatticeECP3 AMC evaluation platform allows designers to investigate and experiment with the features of the LatticeECP3 SERDES and SRIO core in an AMC environment. The board has a single AMC module card edge interface, allowing demonstration of AMC Fat Pipes, and provides a common options interface and a Vita 57.1 FPGA Mezzanine Card (FMC) expansion connector.

The AMC board provides a front-panel Small Form Factor Pluggable (SFP) cage and an RJ45 network interface for 10/100/1000 Ethernet connectivity. The AMC platform is additionally populated with DDR2 and Flash memories to support an on-chip soft processor.

This is a fully integrated platform, with the SRIO hardware and associated demonstration software providing the user the ability to exercise the core out of the box operating at 4x2.5Gbps.

The evaluation package comes with the AMC board, associated cables and an AMC interface card to support both loopback and interoperation with other AMC designs. The demonstration software is fully contained within a SoC environment that also includes the LatticeMico32 32-bit soft processor core, and provides a console user interface via a USB cable connection to a PC, allowing the user to interact with the SRIO core via a menu driven interface.

The software menus provide the ability to configure SRIO parameters, display core status and errors and examine local SRIO configuration registers as well as link partner registers. Also supported are the transfers of various SRIO packet types, such as memory transactions, maintenance read/write transactions and doorbell packets, which act as interrupts to endpoints in
a Serial RapidIO system.

Serial RapidIO 2.1 IP core
The small footprint, Serial RapidIO 2.1 IP endpoint core can be used for processor bridging, control plane interfaces and bridging to legacy interfaces. The core architecture for the Serial RapidIO 2.1 IP core includes the following features:

* Allows for 1x, 2x, 4x lane configurations.
* Up to 3.125Gbps.
* Implements physical layer, transport layer, maintenance transaction handling and error management extensions.
* Provides infrastructure support for external logical layer functions, enabling maximum flexibility.
* Provides a choice of how logic layer functions interact with the rest of the system - SoC bus or packet interfaces.
* Supports software implementations of control plane oriented functions such as doorbells and messages.
* Backward compatible with the v1.3 specification.