Modeling workshop panel brings complexity challenges to forefront

LONDON, UK: The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, held a panel discussion during the GSA & IET International Semiconductor Forum in London on May 18, 2010 titled, “Better Analog Modeling and Integration with iPDKs.”

The panel focused on the status and future directions of compact/SPICE device modeling, Verilog-A standardization and better model optimization and integration with advanced iPDKs. The panel was organized by Paul Double, GSA Analog/Mixed-Signal Interest Group chair in Europe and Wladek Grabinski, MOS-AK/GSA Modeling Working Group manager.

Panelists included Mike Brinson, professor, London Metropolitan University; Slobodan Mijalkovic, senior developer, Silvaco Europe; Doug Pattullo, director, field technical support, TSMC Europe; and Michael Pronath, vice president, product and solutions, MunEDA. The discussion also included academic and industrial organizations directly involved in compact/SPICE model developments, Verilog-A coding and implementation, and modeling support for advanced analog/RF IC designs.

The interactive discussion confirmed general impressions of the importance of Verilog-A as a modeling language and open, standardized development platforms.

"The work being done on Verilog-A standardization via MOS-AK/GSA Modeling Working Group is both timely and significant. In my opinion, one of the most important points to emerge from the panel was the idea that in the real world models should be available at different levels of complexity, but standardized via Verilog-A, and as such be used in situations where they are applicable and computationally efficient.

"As more and more compact simulation models begin to include aspects of different technologies, simulation will move closer to mixed-mode, rather than simply pure analog or pure digital, and selection of model complexity will become paramount for efficient circuit simulation," said Mike Brinson, London Metropolitan University.

"We are witnessing a continuously increasing diversification of compact models with respect to different technologies (SOI, Multi-Gate FETs, TFTs), semiconductor materials (III-V, organic) and application areas (power electronics, high-frequency). The key to successful utilization of such a compact model variety is the standard Verilog-A language providing a shortcut from model developers to circuit designers and avoiding the time-consuming and error-prone manual implementation of compact models into circuit simulators," said Slobodan Mijalkovic of Silvaco Inc.

Verilog-A compact model standardization creates a new form of communication and information exchange at any stage of technology development and IC design; within semiconductor foundries; between CAD tools within design PDK flows; between product development groups responsible for exchange and design reuse; and among virtual component IP providers.

The panel experts agreed that increased involvement from inter-university semiconductor technology service providers, including Europractice and MOSIS, in the promotion of Verilog-A as an open, standardized development platform is needed.

The MOS-AK/GSA Modeling Working Group further commits to these actions and will continue its education mission through a series of the workshops and training courses, with the next event in Tarragona, Spain on June 30 - July 1, 2010.