AHMEDABAD, INDIA: eInfochips Ltd., a leading design services company today announced the availability of Verification Methodology Manual (VMM)-enabled MIPI CSI-2 (Camera Serial Interface), DSI (Display Serial Interface), HSI (High Speed Synchronous Interface) and SDIO Verification IP (VIP).
The eInfochips VIP has also been added to the Synopsys DesignWare Verification IP Alliance Program. The Alliance program gives designers access to a broader range of VMM-enabled verification IP, which complements DesignWare Verification IP portfolio. Synopsys selected and qualified eInfochips for the Alliance program because of its extensive experience in verification, VMM methodology and verification IP development.
“eInfochips has been developing verification IP for many years and has seen an increasing demand for VMM-enabled verification IP for MIPI standards,” said Sribash Dey, VP of Sales at eInfochips. “By working closely with Synopsys to develop VIP that is in accordance with Synopsys’ guidelines and VMM rating tool, our mutual customers can have access to a wider range of VMM-enabled verification IP that helps accelerate their verification process.”
“The addition of eInfoChips’ MIPI and SDIO VIP to the DesignWare VIP Alliance Program further expands the broad range of VMM-enabled verification IP that is complementary to the DesignWare portfolio” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “With eInfochip’s extensive experience in VMM-enabled verification IP, designers can have confidence that the verification IP can be easily integrated into System-Verilog verification environments, helping to speed testbench development efforts.”
eInfochips' VMM-enabled MIPI CSI-2, DSI and HSI, and SDIO VIP products are based on the layered architecture of object oriented programming that allows coverage-driven verification suitable for verifying transmitter and receiver with either of them as the design-under-test (DUT).
MIPI CSI-2 VMM-enabled verification IP
eInfochips’ VMM-enabled MIPI CSI-2 VIP is compliant to the CSI-2 MIPI Specification version 1.0 and draft MIPI Alliance Standard for D-PHY Version 0.85.00. MIPI CSI-2 is an interface between a digital imaging module such as a host processor and image sensor peripheral such as a camera.
The VIP for the MIPI CSI-2 interface can be configured as a Transmitter, Receiver or Monitor. The four-channel VMM-enabled MIPI CSI-2 VIP has fully configurable short and long packets and supports RGB, YUV and RAW long packet data types and short pack synchronization.
The VIP supports directed/constrained/fully random testing mode, monitors and checkers for protocol violations, coverage report generation while allowing configurable transaction generation for each device model.
MIPI DSI VMM-enabled verification IP
eInfochips’ VMM-enabled MIPI DSI VIP is compliant to the DSI MIPI Specification for Version 1.00 and draft MIPI Alliance Standard for D-PHY Version 0.85.00.
MIPI DSI is an interface between a digital imaging module such as a host processor and display peripheral such as an LCD. The MIPI DSI VIP can be configured as a Transmitter, Receiver or Monitor and allows system level verification.
It is a highly configurable, SystemVerilog verification IP that supports four virtual channels, RGB color format for 16bit, 18bit and 24 bit, DCS read/write commands & generic write commands, interleaved and normal frames, bidirectional data transfer and PPI control interface.
The VIP supports fully configurable fields of short and long packets, directed, constrained and fully random testing, coverage report generation and command mode of operation.
MIPI HSI VMM-enabled verification IP
eInfochips’ MIPI HSI VMM-enabled VIP is compliant with the version 1.01.00 specification. MIPI HSI is an interface between an applications processor and cellular modem. The MIPI HSI VIP can be used for system level verification of DUT MIPI HSI transmitter and/or receiver and for functional coverage generation.
The highly configurable, VMM-enabled SystemVerilog verification component supports synchronized/pipelined/receiver data flows and stream/frame transmission modes. Other features of MIPI HSI VIP are error injection, functional coverage, random as well as user-defined configuration and run-time configurability.
SDIO VMM-enabled verification IP
eInfochips’ VMM-enabled SDIO HOST VIP allows coverage-driven verification and can be configured as IO-aware or non IO-aware to verify SDIO card, SD memory card, SD Combo card and SD Multimedia Card (MMC).
The VIP is compliant to the SD Host Specification 1.0, SD Specification 1.10 and 2.00 and to the SDIO Specification 1.2. It offers support for single slot operation, card detection, re-initialization of combo card, 1/4/8 bit SD bus mode and SPI bus mode, low/full/high speed, stream transfer and direct command during data transfer.
The VIP also facilitates functional coverage, card suspend/resume/lock/unlock operations, protocol and transaction level checking and plug-and-play operations.
Deliverables
Deliverables include verification IP encrypted code, sample test bench and test cases, user guide and release notes. eInfochips provides regular product updates and technical support. MIPI CSI-2, HSI, DSI and SDIO VMM-enabled VIP products are now available.
Showing posts with label VMM. Show all posts
Showing posts with label VMM. Show all posts
Tuesday, June 30, 2009
Wednesday, June 3, 2009
eInfochips' DDR2 SDRAM SystemVerilog and VMM based memory model generator tool
AHMEDABAD, INDIA: eInfochips Inc., a leading IP driven ASIC/FPGA/SoC, Embedded Systems & Software design services company has announced the availability of DDR2 SDRAM SystemVerilog VMM (Verification Methodology Manual) based Memory Model Generator.
This HVL based tool is an integrated solution to generate behavioral models for all leading memory vendors such as Micron, Samsung, Hynix and Elpida, thereby shortening verification time & maximizing memory coverage.
“We are very pleased to announce the DDR2 SDRAM SystemVerilog & VMM based behavioral memory model generator tool that offers high-quality simulation models and verification environments,” states Nirav Shah, Director of Marketing at eInfochips. “We always look for solutions that add value to the overall development and benefits industry. This tool will be exceptionally beneficial to ASIC/Chip/SoC level verification teams and memory controller IP developers.”
With eInfochips’ DDR2 SDRAM model generator, it is possible to configure parameters of DDR2 SDRAM memory such as memory size, data width, clock rate, cycle time, CAS latency and data rate.
Key features of memory generator tool
The DDR2 SDRAM memory generator is a TCL/TK based tool that supports leading memory vendors like Micron, Samsung, Hynix and Elpida, and preserves a large library of part numbers for each supported memory vendor.
The tool can be operated in two modes -– typical mode or custom mode. In the typical mode, a user may choose vendors and part numbers to generate the memory model. In the custom mode, a user may create customized behavioral model from scratch by configuring parameter of DDR2 SDRAM through the configuration selection algorithm (CSA).
Key features of generated behavioral models
The behavioral models are compliant to JEDEC standard JESD79 -– 2D and ready to be plugged into Verification Environment. The models offer in-built coverage and can be configured to turn On/Off initialization, enable/disable DDR2 interface checkers and coverage.
Deliverables include completely verified SystemVerilog VMM based DDR2 SDRAM generator encrypted code, user guide and release notes. The DDR2 SDRAM SystemVerilog VMM based memory generator tool is now available and comes with support. Currently the tool supports DDR2 but is expandable to support DDR, DDR3, NAND Flash, NOR Flash, QDR, XDR.
This HVL based tool is an integrated solution to generate behavioral models for all leading memory vendors such as Micron, Samsung, Hynix and Elpida, thereby shortening verification time & maximizing memory coverage.
“We are very pleased to announce the DDR2 SDRAM SystemVerilog & VMM based behavioral memory model generator tool that offers high-quality simulation models and verification environments,” states Nirav Shah, Director of Marketing at eInfochips. “We always look for solutions that add value to the overall development and benefits industry. This tool will be exceptionally beneficial to ASIC/Chip/SoC level verification teams and memory controller IP developers.”
With eInfochips’ DDR2 SDRAM model generator, it is possible to configure parameters of DDR2 SDRAM memory such as memory size, data width, clock rate, cycle time, CAS latency and data rate.
Key features of memory generator tool
The DDR2 SDRAM memory generator is a TCL/TK based tool that supports leading memory vendors like Micron, Samsung, Hynix and Elpida, and preserves a large library of part numbers for each supported memory vendor.
The tool can be operated in two modes -– typical mode or custom mode. In the typical mode, a user may choose vendors and part numbers to generate the memory model. In the custom mode, a user may create customized behavioral model from scratch by configuring parameter of DDR2 SDRAM through the configuration selection algorithm (CSA).
Key features of generated behavioral models
The behavioral models are compliant to JEDEC standard JESD79 -– 2D and ready to be plugged into Verification Environment. The models offer in-built coverage and can be configured to turn On/Off initialization, enable/disable DDR2 interface checkers and coverage.
Deliverables include completely verified SystemVerilog VMM based DDR2 SDRAM generator encrypted code, user guide and release notes. The DDR2 SDRAM SystemVerilog VMM based memory generator tool is now available and comes with support. Currently the tool supports DDR2 but is expandable to support DDR, DDR3, NAND Flash, NOR Flash, QDR, XDR.
Friday, May 1, 2009
Verivue deploys VMM and Synopsys VCS solution
MOUNTAIN VIEW, USA: Synopsys Inc. announced that Verivue, Inc. has standardized on the production-proven VMM verification methodology and VCS functional verification solution, both key components of Synopsys' Discovery Verification Platform, for the verification of their flagship product, the MDX 9000 Series Media Distribution Switch.
The VMM-based approach allows Verivue to implement a transaction-based verification methodology that provides reusable test environments for higher test coverage, ease-of-use and scalability from block to system-level. The combination of the VCS solution and VMM enables faster turn-around with accelerated compile times and optimized performance for system designs, contributing to a productivity boost of up to 4x over traditional approaches.
A major benefit of VMM-based verification environments is verification reuse. With VMM, Verivue is able to create fifteen "plug-and-play" transaction models that can generate large volumes of data. Engineers are able to boot the entire system as soon as the hardware becomes available. Additionally, the VMM Applications, such as Register Abstraction Layer (RAL), speed up and simplify verification.
"With hundreds of successful deployments in highly complex verification environments, VMM is the most widely used verification methodology," said Swami Venkat, senior director of Marketing in the Verification Group at Synopsys. "Engineers using VMM and VMM Applications consistently achieve higher quality verification results and greater verification productivity, as evidenced in a large number of VMM user papers and tape-outs. Synopsys continues to invest in verification methodology innovations with new technologies such as the VMM for Low Power to address complex functional verification challenges."
The VMM-based approach allows Verivue to implement a transaction-based verification methodology that provides reusable test environments for higher test coverage, ease-of-use and scalability from block to system-level. The combination of the VCS solution and VMM enables faster turn-around with accelerated compile times and optimized performance for system designs, contributing to a productivity boost of up to 4x over traditional approaches.
A major benefit of VMM-based verification environments is verification reuse. With VMM, Verivue is able to create fifteen "plug-and-play" transaction models that can generate large volumes of data. Engineers are able to boot the entire system as soon as the hardware becomes available. Additionally, the VMM Applications, such as Register Abstraction Layer (RAL), speed up and simplify verification.
"With hundreds of successful deployments in highly complex verification environments, VMM is the most widely used verification methodology," said Swami Venkat, senior director of Marketing in the Verification Group at Synopsys. "Engineers using VMM and VMM Applications consistently achieve higher quality verification results and greater verification productivity, as evidenced in a large number of VMM user papers and tape-outs. Synopsys continues to invest in verification methodology innovations with new technologies such as the VMM for Low Power to address complex functional verification challenges."
Tego standardizes on VMM and Synopsys VCS Solution to speed RFID tags verification
MOUNTAIN VIEW, USA: Synopsys Inc. announced that Tego, Inc. has standardized on the production-proven VMM verification methodology and VCS® functional verification solution, both key components of Synopsys' Discovery Verification Platform, to verify its radio frequency identification (RFID) tags for the aviation industry.
Tego's RFID tags, which are used to store intelligent data directly on an object without the need for battery power, have grown increasingly complex due to memory limitations and, therefore, require a robust verification solution to accelerate the design cycle. Tego chose a VMM-based approach to address the increased chip complexity, higher test volume and ease-of-use requirements. They have also standardized on the VCS solution to optimize performance, bug detection and capacity. The combined solution enabled Tego to achieve first-pass silicon success on its next-generation passive RFID tag and will help the company to hit ever-narrowing time-to-market windows on future projects.
A major benefit of VMM-based verification environments is easier customization. With VMM, Tego is now able to create a customized, "plug-and-play" testbench environment that can run data collection and comparison separately. Engineers are able to generate specific corner scenarios or collect functional coverage for particular test scenarios and generate new test cases without having to modify the entire testbench unnecessarily. Additionally, the VMM-based environment allows reuse of the pre-existing golden reference model, initialization routines and protocol-dependent monitoring logic, improving productivity and streamlining time-to-market for future designs.
Tego's RFID tags, which are used to store intelligent data directly on an object without the need for battery power, have grown increasingly complex due to memory limitations and, therefore, require a robust verification solution to accelerate the design cycle. Tego chose a VMM-based approach to address the increased chip complexity, higher test volume and ease-of-use requirements. They have also standardized on the VCS solution to optimize performance, bug detection and capacity. The combined solution enabled Tego to achieve first-pass silicon success on its next-generation passive RFID tag and will help the company to hit ever-narrowing time-to-market windows on future projects.
A major benefit of VMM-based verification environments is easier customization. With VMM, Tego is now able to create a customized, "plug-and-play" testbench environment that can run data collection and comparison separately. Engineers are able to generate specific corner scenarios or collect functional coverage for particular test scenarios and generate new test cases without having to modify the entire testbench unnecessarily. Additionally, the VMM-based environment allows reuse of the pre-existing golden reference model, initialization routines and protocol-dependent monitoring logic, improving productivity and streamlining time-to-market for future designs.
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