Synopsys accelerates development of SoC designs with IP solution for PCI Express 3.0

MOUNTAIN VIEW, USA: Synopsys Inc. today announced its complete DesignWare IP solution for PCI Express (PCIe) 3.0 consisting of digital controllers, PHY and verification IP. PCI Express 3.0 is the next generation of the PCI Express I/O standard, which is currently under development within the PCI Special Interest Group (PCI-SIG) at a preliminary revision 0.5.

Synopsys' high-quality DesignWare IP enables easy integration of the 8.0 GT/s PCI Express 3.0 interface into system-on-chips (SoCs) for high-performance enterprise computing applications.

Built on the trusted DesignWare IP for PCI Express 2.0 and 1.x architecture, which has been silicon-proven in more than 250 SoC designs, the DesignWare IP for PCI Express 3.0 allows designers to quickly incorporate the new PCI Express 3.0 features into their products with less risk and improved time to market.

For over 15 years, Synopsys has consistently been a technology leader in PCI and PCI Express IP. Synopsys' work with leading technology companies in the PCI Express ecosystem has led to a number of key contributions to the industry, including the release of the industry's first complete PCI Express 2.0 IP solution.

In addition, the DesignWare IP for PCI Express with PCI-SIG Single Root I/O Virtualization (SR-IOV) Technology was used as the gold standard in the SR-IOV lab at the 2008 Intel Developers Forum to showcase SR-IOV technology.

Synopsys is continuing this technology leadership and leveraging its expertise to provide early availability of the PCI Express 3.0 IP, enabling designers to develop products in conjunction with the ongoing development of the PCI Express 3.0 specification and deliver compliant products soon after the initial public release of the specification.

"Synopsys has been an active member of the PCI-SIG since 2003, participating in the working groups and contributing to the evolution of the PCI Express specification," said Al Yanes, PCI-SIG chairman and president. "As a provider of PCI Express IP, Synopsys supports the latest version of the PCI Express 3.0 specification to help facilitate the early adoption of PCI Express 3.0 into the enterprise computing market segment."

Synopsys invests significantly to ensure the DesignWare IP for PCI Express is interoperable with other PCI Express-based products in the market. As a result, Synopsys' DesignWare IP for PCI Express is used in Agilent's Protocol Test Cards (PTC), a required Gold Test at the PCI-SIG compliance workshops.

The DesignWare IP is also the first IP to pass Agilent's Jammer in-line error injection testing, which injects disruptive test scenarios to test the reliability and robustness of the PCI Express design.

Using Synopsys' high-quality development methodology helps ensure the new DesignWare IP solution for PCI Express 3.0 provides the same level of interoperability and strict adherence to the PCI Express standard as the existing DesignWare IP for PCI Express solutions.

"Neterion is at the forefront of developing high-performance products for the enterprise computing market and PCI Express is a key technology for our product roadmap," said Dennis Shwed, vice president of hardware development at Neterion.

"We have been very successful in incorporating the Synopsys DesignWare IP for PCI Express in our current products and are excited to see Synopsys aggressively embrace PCI Express 3.0. This is exactly what we have come to expect from an industry leader like Synopsys."

Synopsys' suite of digital controllers for PCI Express 3.0 is based on the DesignWare IP for PCI Express 2.0/1.1 architecture, allowing designers to benefit from small area and low latency to reduce costs and improve overall system throughput. The DesignWare digital controllers for PCI Express 3.0 implement the same interfaces as PCI Express 2.0, allowing customers to quickly upgrade to PCI Express 3.0.

For the physical layer, Synopsys is developing a PHY architecture specifically optimized for PCI Express 3.0 with high-performance margins to allow the PHY to achieve the final PCI Express 3.0 specifications in areas such as jitter, margin, and receive sensitivity.

In addition, the advanced built-in diagnostic capabilities and ATE test vectors enable at-speed product testing of the DesignWare PHY IP for PCI Express 3.0 and on-chip visibility into the actual link performance.

Complementing the digital controllers and PHY is the DesignWare Verification IP for PCI Express 3.0, which supports directed testing and constrained random methodologies defined in the Verification Methodology Manual (VMM) for SystemVerilog and allows designers to create complex protocol test scenarios for verifying their SoCs.

"The enterprise computing market is driving the need for the high-performance PCI Express 3.0 interface in the products our customers expect to be shipping in 2010," said John Koeter, vice president of marketing for the Solutions Group at Synopsys.

"By providing designers with early access to PCI Express 3.0 IP that is based on a proven and trusted architecture, Synopsys lowers the risk of incorporating the PCI Express 3.0 interface into advanced SoCs."

The DesignWare digital controllers and Verification IP for PCI Express 3.0 are available now for selected early adopters. The DesignWare PHYs for PCI Express 3.0 are currently in development for leading foundry processes.

Avery support for PCI Express 3.0 verification IP

ANDOVER, USA: Avery Design Systems Inc., an innovator in functional verification productivity solutions, announced that its PCI-Xactor verification IP solution now supports the PCI Express (PCIe) 3.0 draft standard, at a preliminary revision 0.5, and is available to existing customers under active maintenance.

PCI-Xactor from Avery Design allows customers to increase verification productivity and confidence in designs targeting the evolving PCIe 3.0 standard which delivers 8.0 GT/s performance and advanced features for the graphics, server, network and computer markets.

“PCI Express 3.0 warrants critical design updates to the PHY layer of the PLX family of switch devices, and getting this correct the first time is an absolute necessity given our critical time-to-market windows,” said Vijay Meduri, Vice President of Engineering, PLX Technology. “Avery is one of our important partners in ensuring interoperability with the ecosystem.”

"IP products for verification of PCI Express systems, such as those from Avery Design Systems, offer significant value to the PCI-SIG community," said Al Yanes, PCI-SIG Chairman and President.

"Avery Design has been an active participant in the PCI Express design ecosystem for several years, and we appreciate their contributions, which help to streamline the deployment of PCI Express technology into the industry."

"Avery is a trusted partner in the development of our PCI-Express PHY and Controller IP products. We use Avery's PCI-Xactor Verification IP, as do our customers, for validating operation and compliance," said Ewald Liess General Manager of Snowbush IP, a Division of Gennum.

"The timely release of PCIe 3.0 support in PCI-Xactor is an important element that helps our validation and supports the emerging 3.0 ecosystem."

Avery’s PCI-Xactor is a complete functional verification solution for PCI Express 1.1/2.1/3.0 and SR-IOV including feature rich models that work in any verification languages including SystemVerilog OVM and VMM methodologies, comprehensive protocol checking, functional coverage monitoring, and dedicated core and chip-level compliance test suites for Root Complex, Endpoint, SR-IOV Endpoint, Switch, and PHY designs.

"We are committed to work with our chip and systems customers and IP partners to provide a total chip, controller, and PHY verification solution for the evolving PCIe 3.0 standard to lower their risk and time to market associated with bringing next generation products to market, while delivering robust and superior solutions," said Chris Browy, Vice President of Avery Design Systems.