Tuesday, August 31, 2010

Advantest selects Calypto’s power optimization and verification tools to reduce power in ASIC designs

SANTA CLARA, USA: Calypto Design Systems Inc., the leader in sequential analysis technology, announced that Advantest Corp., a premier supplier of semiconductor test equipment, has adopted its PowerPro CG (clock gating) and SLEC Pro products to optimize power in its ASIC designs.

Calypto offers the industry’s leading RTL power optimization and formal verification solutions, enabling significant ASIC power reduction while shortening design time and improving design quality.

“Our ASIC design teams are under extreme pressure to deliver low power solutions, and we are very impressed with the outstanding results we have seen from PowerPro CG and SLEC Pro in our design flow,” said Hiroshi Kobayashi, general manager of Design Management Division, Advantest. “They are the only tools in the industry that are based on sequential analysis and offer fully automated RTL power optimization with an integrated, comprehensive verification flow.”

Based on Calypto’s patented sequential analysis technology, PowerPro CG evaluates circuit behavior across multiple clock cycles to identify sequential clock gating opportunities and creates the required sequential clock-gating enable logic to reduce design power. PowerPro CG then generates new power-optimized RTL that is identical to the original RTL except for the surgical insertion of the sequential clock-gating enable logic.

SLEC Pro comprehensively verifies the power-optimized RTL generated by PowerPro. SLEC Pro is a formal, functional sequential logic equivalence checker that ensures functional equivalence between the original RTL design and the corresponding power-optimized RTL design for all possible input sequences.

“Advantest is committed to providing leading automatic test equipment for the semiconductor industry,” said Tom Sandoval, chief executive officer of Calypto. “PowerPro CG and SLEC Pro will enable Advantest to incorporate advanced, ultra-low power ASICs into its products in the shortest possible time.”

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