Mentor Graphics works with TSMC to speed SoC verification with Calibre automatic waivers

WILSONVILLE, USA: Mentor Graphics Corp. announced that Taiwan Semiconductor Manufacturing Corp. (TSMC) has completed technical validation of the Calibre Automatic Waivers solution and is in the process of adopting it to speed verification of large SoCs.

The new facility allows TSMC, their IP ecosystem, and customers to attach design rule checking (DRC) waivers to their IP datasets so that waived violations will not appear during verification runs. This cuts down on DRC debugging as well as unnecessary interactions between the designer and TSMC for previously waived IP, reducing the time to tapeout.

Customers have seen an order of magnitude reduction in time required to review false (waived) DRC violations in large SoC designs after adoption of the Calibre Automatic Waivers flow. TSMC is planning to use Calibre Automatic Waivers with TSMC-developed IP.

ST Juang, senior director of Design Infrastructure Marketing at TSMC, said: “This solution allows users to identify and suppress DRC error results in IP if they meet appropriate criteria defined by the foundry. This saves our customers significant debug time, without the risk of accidentally waiving true errors. Unlike previous approaches, the Calibre solution accurately accounts for waivers across cell hierarchies without placing a significant burden on the user.”

For example, users at MediaTek Inc. find it is common to have hundreds or thousands of DRC violations in IP at the chip level resulting from design rules that have previously been reviewed and waived by the foundry.

The company reports that previously a significant amount of time was spent unnecessarily reviewing each waiver violation simply because there was no efficient way to transfer the waiver information along with the IP when it is incorporated into a design. The Calibre Automatic Waivers solution is now being used by MediaTek to efficiently capturing waivers at the time they are approved, allowing waiver violations to be automatically and accurately removed from DRC results, which significantly reduces debug time.

“Communicating waivers between the design and foundry teams can be a big time sink, and it’s easy to inadvertently lose information in the process,” said Mark Judiscak, CAD Director at Microchip Technology Inc.

“By incorporating waiver information directly into the IP datasets, it becomes available wherever the IP is used. Not only does the designer save debug time that is typically wasted reviewing false DRC violations, but the foundry team also has immediate visibility into exactly which results were waived for a given DRC rule. This greatly expedites communication and resolution of issues.”

“Our customers have been asking for a solution to this problem, which is growing as SOC designers make more and more use of external IP in order to add more functionality and speed their time to market,” said Joseph Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics.

“This productivity enhancer is one of the many ways we continue to add value to maintain Calibre’s position as the industry’s most popular physical verification platform.”