SEOUL, SOUTH KOREA: MagnaChip Semiconductor Ltd, an Asia-based designer and manufacturer of analog and mixed-signal semiconductor products, announced that it now offers an enhanced process design kit (PDK) for 0.18um and 0.35um BCD (bipolar CMOS-DMOS) technology which has been receiving industry-wide attention.
The latest PDK features major advancements from three key perspectives: user environment, PDK content and design support. More specifically, functions such as one click download, PDK installer and auto-version matching enable rapid automatic setup of PDK conditions, creating a user friendly environment.
In terms of PDK content, ESD (electrostatic discharge) protection Pcell (parameterized cell) was added to enable engineers who are not familiar with ESD or rule deck to easily select menu-driven rule deck options such as DRC (design rule check) and LVS (layout versus schematic), for their design.
Also, tables for SOA (safe operating area) are set up for each device to prevent designers from inadvertently applying device operating conditions during their design efforts. In addition, a SPICE library handling utility is provided for trouble-free selection of corner mode for each device group during circuit simulation.
For enhanced design support, a schematic migration utility is offered for simple importing of previous PDK designs to the new PDK environment. A layout utility is also provided to support global net connection, seal ring and guard ring. As a result of these updates, including support for MTP (multi-time programmable) cell and IP design, the BCD PDK environment is greatly improved.
TJ Lee, senior VP of MagnaChip's Semiconductor Manufacturing Services Engineering, said: "We are very pleased to announce the offering of an enhanced process design kit for our 0.18um and 0.35um BCD technology. With this and future innovations, we will continue to work to meet the increasing demand for designer-friendly environments for our customers."
Friday, June 11, 2010
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