E-System Design announces new breakthrough for 3D interconnect parasitic extraction

DAC 2010, ANAHEIM, USA: E-System Design, Inc. will present a new breakthrough method for 3D interconnect extraction at the Global Semiconductor Alliance’s (GSA) 3D-IC DESIGN TOOLS & SERVICES meeting June 15th from 6:30-8:00pm.

Based upon technology developed at the Georgia Institute of Technology, Package Research Center, E-System Design is developing an analysis tool capable of full wave parasitic extraction of hundreds or as will be needed soon, thousands of interconnects simultaneously.

As the number of interconnects grows dramatically with the advent of 3D, it is no longer possible to avoid considering their coupling effects on signal integrity and the power distribution network. The traditional methods for parasitic extraction of one or two interconnects at a time and simulating signal and power integrity performance have become obsolete.

“3D structures require tools that are not only accurate but can work with thousands of TSVs, many of today’s ‘solutions’ can only analyze a few TSVs before they run out of gas,” said Madhavan Swaminathan, CTO, founder of E-System Design. “In our analysis and published papers, the proximity and skin effects are significant in TSV arrayed structures. If not properly extracted and analyzed, designers can be misled.”

When released, 3D EXT will support all types of interconnects, including wire bond, column grid and via arrays, and through silicon vias (TSVs) used in IC’s and silicon interposers to create the latest generation of consumer devices. The output is a standard Touchstone file or RLGC information that can be directly input to Sphinx for Signoff for frequency simulation or converted to Spice with Idem Plus for simulation in any customer preferred spice timing based simulator.

3D EXT is currently in working prototype form. E-System Design can provide design services, and welcomes interest from potential customers and partner companies.

“Whether an extractor can accurately extract a tiny handful of these structures is not the question, the real issues are accuracy and the time and resources required to complete an extraction with many such structures,” said John Sovinsky, CTO, CAD-Design Services.

“Given the costs required to develop 3D stacked die and packaging products, developers need to ensure that all interconnects are accurately extracted and analyzed: We are pleased to be working with E-System Design to develop a seamless set of tools that encompasses product development from concept, design, layout, analysis and simulation to production ready, electrically validated output for high performance 2D and 3D electronic packaging, printed circuit boards and systems.”