SAN JOSE & SANTA CLARA, USA: Altos Design Automation Inc. and Extreme DA have jointly developed an essential signal-integrity (SI) design flow for integrated circuit (IC) designs manufactured at process nodes of 65-nanometers (nm) and below.
Mutual customers of both companies have verified successful SI static timing analysis using Altos’ Liberty models with the Extreme DA GoldTime analyzer.
SI timing analysis required
A SI noise-aware design flow is required for effectively managing the crosstalk delay and glitch noise found in the dense and complex ICs manufactured in current nanometer-scale silicon technology nodes.
The SI-aware flow, featuring advanced current source models (CCS), enables designers to accurately account for these noise effects. It eliminates the need for designers to use separate analysis tools and proprietary noise models that require lengthy characterization.
The accuracy of the underlying cell library used by GoldTime to predict the effects of crosstalk delay and glitch noise on a design’s timing and yield is essential for success. The development of this verified flow has qualified Altos as an Extreme DA-approved source for the SI-aware libraries required by GoldTime.
“We have worked with Extreme DA to validate Liberate’s CCS noise-aware timing models with GoldTime timing analysis,” said Jim McCanny, Altos CEO. “We are committed to ongoing support of any advanced requirements that GoldTime users may have in the future.”
"Noise accurate timing analysis relies on detailed characterization of the cell libraries used by designers," said Mustafa Celik, president and CEO of Extreme DA. "Our collaboration with Altos has produced a powerful, verified SI flow that can improve IC quality, increase yields, and accelerate time to market.”
Extreme DA GoldTime for use with Altos Variety and Liberate models is available now from Extreme DA. Pricing varies depending on configuration. Altos Variety and Liberate approved libraries for Extreme DA GoldTime are available now from Altos.
Friday, June 11, 2010
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