eASIC announces new ASIC-in-a-box design kits

SANTA CLARA, USA: eASIC Corp., a provider of NEW ASIC devices, announced the immediate availability of two ASIC-in-a-Box design kits that enable ASIC design to be widely accessible and thereby reverse the trend of declining ASIC design starts.

Through simplifying the design flow, the design kits empower engineers who are unfamiliar with ASIC design to now complete designs at a fraction of the cost and time compared to traditional standard cell ASICs.

Nextreme NEW ASICs are uniquely constructed to help simplify design, verification and silicon processing steps within the overall flow. Designers are able to focus their effort mainly on achieving their desired functionality and timing and not on arduous complex tasks such as power mesh design, signal integrity, test insertion, clock insertion, STA, ATPG, formal verification and LVS/DRC as they do with traditional standard cell ASICs.

The NEW ASIC-in-a-Box design kits provide software and documentation for completing and implementing Nextreme chip designs, and also deliver board design and debug guidelines for designing systems that incorporate Nextreme devices.

“Our NEW ASIC-in-a-Box design kits dispel the myth that ASICs are difficult, risky and expensive to design,” commented Jasbinder Bhoot, Vice President of Marketing at eASIC.

“eASIC has completed over 100 tape outs and delivered over 100 prototype designs in less than two years using the flow and tools that are now available in the ASIC-in-Box kits. Our new design kits make ASIC design affordable, accessible and achievable for everyone.”

Design kit contents
The NEW ASIC-in-a-Box Design Kits contain the following items:

* eASIC’s eTools software suite that includes easy to use utilities for configuring PLLs/clocks, assigning pins/pads, generating memories and post placement configuration and DRC.
* Magma DA’s Blast RTL software for performing synthesis and placement.
* Documentation and design tutorials to accelerate design implementation.
* JTAG programming cable for configuration and debug.
* Technical support website access.

eASIC, IPextreme announce Freescale ColdFire processors for Nextreme NEW ASICs

SANTA CLARA, USA: eASIC Corp., a provider of NEW ASICs devices, and IPextreme, the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, announced the immediate availability of Freescale’s 32-bit V1 and V2 ColdFire processor cores for Nextreme NEW ASICs.

The addition of the ColdFire processors to eASIC’s eZ-IP core library, enables designers to implement small foot-print, ColdFire cores on fast turnaround Nextreme NEW ASICs and thus provide a low-cost entry point for creating customized ColdFire-based applications within consumer, medical, automotive, and industrial markets.

With almost three times greater performance of comparable implementations in low-cost FPGAs, Nextreme NEW ASICs provide system designers with a significantly better price/performance alternative to FPGA implementations and with a much lower up-front cost alternative to standard cell ASIC implementations.

The 32-bit RISC V1 and V2 ColdFire processors are backed by a complete and proven ecosystem of development tools, software stacks, and drivers from Freescale and other leading providers such as GNU, Green Hills Software, Wind River Systems, Accelerated Technology / Mentor Graphics, and many others.

“The inclusion of V1 and V2 ColdFire processors into our eZ-IP portfolio enables embedded system designers to leverage their existing code-base while quickly delivering optimized, highly differentiated, low-cost solutions that can be taken into high-volume production,” said Jasbinder Bhoot, Vice President of Worldwide Marketing at eASIC. “We want our customers to have the freedom to choose the right processor core for the task at hand, and not forced into a proprietary offering as we see with some FPGA vendors,” added Bhoot.

“The V1 and V2 ColdFire synthesizable IP cores are two of our most popular processors and we are excited to add them to eASIC’s eZ-IP core library,” said Rick Tomihiro, Vice President of Marketing at IPextreme. “Thousands of embedded systems designers worldwide create designs around the ColdFire architecture and enabling them to combine the high performance, low gate count and complete ecosystem of ColdFire microprocessors with the low cost and high performace of eASIC’s Nextreme NEW ASICs provides them with a unique advantage over their competition to create advanced and low cost embedded solutions to meet and exceed their customers requirements.”

Deliverables
The V1 and V2 ColdFire cores for the Nextreme NEW ASICs are available from IPextreme. The cores are delivered in Verilog source RTL and include:

* Synthesizable Verilog source code.
* Integration testbench and tests.
* Documentation.
* Scripts for simulation and synthesis with support for all common EDA tools.

ARM uses eASIC devices to validate Cortex-A9 MPCore multicore processor-based devices

SANTA CLARA, USA: eASIC Corp. a provider of low up-front development cost NEW ASICs, announced that ARM has successfully validated its next-generation Cortex-A9 MPCore multicore processor using eASIC’s Nextreme NEW ASICs.

With Nextreme, ARM was able to perform at speed verification with significantly higher performance, and lower development cost compared to the high-end FPGA solution that was previously used.

The Cortex-A9 MPCore multicore processor is the latest in a strong portfolio of CPU cores now being designed-in across wireless, networking, consumer and home applications.

The processor core integrates proven ARM® MPCore technology along with further enhancements to simplify and broaden the adoption of multi-core solutions and extending peak performance to unprecedented levels, while reducing power consumption at the processor and system level. Nextreme’s fast logic fabric, dedicated memories and single Via-based interconnect were able to provide the performance required to fully test the new Cortex-A9 processor.

“We were able to develop our eASIC device in a reduced time and cost of a standard cell ASIC and with development costs that were even lower than an FPGA approach and the eASIC device worked right first time on our PBX-A9 validation and development board,” said John Goodacre, Director, Program Management of ARM Processor Division. “We see the 90nm Nextreme eASIC technology as a very cost effective way of validating and demonstrating new products to our customer base and getting them to market much earlier.”

“In addition to the growing acceptance from traditional FPGA and ASIC users, we also see considerable interest from conventional ASSP companies and IP providers who see eASIC technology as a way of developing at speed verification solutions that can even be taken into volume production,” said Jasbinder Bhoot, Vice President of Marketing, eASIC Corporation. “As process geometries shrink, eASIC will become one of the few practical solutions to perform at speed verification of IP cores and ASSPs.”

eASIC accelerates DSP market with new IP cores

SANTA CLARA, USA: eASIC Corp., a provider of NEW ASIC devices, announced the immediate availability of two new DSP IP cores, an FFT and FIR Filter Compiler, to accelerate it’s growing momentum into the high performance DSP market.

The new FFT core, available from eASIC, supports point sizes from 16 to 16K points and data rates up to 100 MSPS with a compact footprint. The FIR Compiler core, available from eZ-IP Alliance partner Steepest Ascent can process data streams as high as 500 MSPS and with its optimized multiplier-less architecture is perfectly suited to Nextreme and Nextreme-2 architectures.

The addition of mainstream DSP blocks to eASIC’s IP portfolio makes it easier for wireless and video/imaging system designers to rapidly migrate costly FPGA-based DSP designs to lower-cost, lower-power Nextreme Series NEW ASICs.

FFT and FIR filters are the most widely used algorithms in digital communications and video/imaging systems. The new FIR Filter Compiler enables designers to generate optimal implementations of single or multi-rate filters and also takes advantage of multichannel applications.

Most importantly, the optimized multiplier-less architecture greatly reduces resource usage, boosts performance and eliminates the need for large amounts of hard multipliers typically found in FPGAs today. The FFT core provides optimal implementations for OFDM Wireless systems like LTE & WiMAX. Both IP cores support Nextreme and Nextreme-2 NEW ASICs.

“Many wireless infrastructure and video/imaging designers that are using FPGAs are desperately looking for ways to significantly reduce cost and power consumption of their systems,” said Jasbinder Bhoot, Vice President of Marketing at eASIC. “This new IP portfolio will make it much simpler and quicker for customers to migrate their expensive and power hungry FPGA-based DSP designs to Nextreme Series NEW ASICs and reduce both power consumption and cost.”

“The DSP market like many others is currently declining. The availability of lower-cost design platforms is a must to help manufacturer’s lower costs and deliver affordable products into the market,” said Will Strauss, President of Forward Concepts. “The addition of these DSP IP cores as part of eASIC’s Nextreme-2 ASIC library will help designers to deliver low cost products faster.”