Synfora intros PICO Extreme Power for low power applications

MOUNTAIN VIEW, USA: Synfora Inc., the premier provider of algorithmic synthesis tools for IC and system designers of large, complex processing applications, announced PICO Extreme Power to reduce power consumption, which is a major consideration in designing mobile devices.

The new PICO Extreme Power is the industry’s first algorithmic synthesis tool to automatically minimize power consumption at the system-level based on a variety of techniques, including automatic multi-level clock gating insertion.

Multi-level clock gating enables clock gating to be applied to a computation block in an application accelerator at any level in the hierarchy. PICO Extreme Power has delivered savings of up to 50 percent using this technique.

Researchers at Rice University were amongst the first users of PICO Extreme Power and designed and evaluated a low-density parity check (LDPC) decoder for the next generation wireless handset SoC. They demonstrated a 23.5 percent reduction in dynamic power over an identical design using a standard flow.

Similarly, the Indian Institute of Science (IISc) evaluated the effectiveness of the approach using eight complex applications from video, imaging and wireless domains. The results indicate as much as 50% savings in dynamic power for executing a single task in some of the applications and as much as 30% savings while executing a large number of tasks. The average power reduction over all applications was 22% for a single task and 15% over multiple tasks.

“Introducing power minimization at the system or architecture level has a greater impact on power consumption than that implemented at the RTL or circuit level, and adding architecture-level power optimization capabilities to a high-level algorithmic synthesis tool can provide significant benefits for low-power IC designs,” said Prof. Joseph Cavallaro, Rice University. “The results of our research clearly demonstrate that the clock gating capabilities available with the PICO Extreme Power tool can be a major contributor to decreasing power consumption.”

In two additional designs generated using PICO Extreme Power, RTL level power estimates done with the Atrenta SpyGlass-Power solution, showed power reductions of 16 percent and 53 percent compared with designs without block-level clock gating.

“Using SpyGlass-Power in conjunction with PICO Extreme Power enables designers to manage power consumption early in the design and ensure that the power savings can be measured before the generated RTL goes to implementation. This flow has the potential to make significant improvements in the power efficiency of SoCs,” said Piyush Sancheti, senior director of business development at Atrenta.

In traditional RTL (Register Transfer Language) design methodologies, inserting clock gating at a block level is usually a manual effort because it requires the knowledge of when the block is inactive. Using PICO Extreme Power, the designer uses directives to specify where to insert clock gating, and PICO does the rest automatically.

As a result, PICO Extreme Power allows designers to retain all the productivity benefits of automated synthesis and verification, including reduced design and verification time and the ability to react very rapidly to changes in the design specification, while optimizing the IC power consumption.

PICO platform
The PICO Algorithmic Synthesis Platform provides productivity gains by creating application accelerators from an untimed C algorithm at the highest level of abstraction. PICO yields QoR (quality of results) that is competitive with manual design by using a unique parallelizing compiler and multi-level hierarchical abstraction and IP reuse.

It offers the highest possible level abstraction for large designs, and has been proven to provide huge productivity gains on the largest production designs, not just on small blocks.

India leads world in semicon: S. Janakiraman

Irrespective of the debate raging within the semicon community regarding the IC wafer fabs in India, the strength of and the talent within the Indian semiconductor industry has never ever been in doubt.

Delivering the welcome note at the recently held ISA Technovation 2008 awards ceremony at the Indian Institute of Science, S. Janakiraman, the former Chairman - India Semiconductor Association, and President & CEO – R&D services, MindTree Ltd, elaborated the fact that India now leads the world through execution of most complex and latest technology designs.

Former president of India, Dr. APJ Abdul Kalam was the Chief Guest at the function.

Commenting on the ISA's role, Janakiraman said that it has been an industry driven body focused on the unique needs and progress of the semiconductor and related industries in India to make it vibrant and project India as a global leader. The ISA's journey began four years back, in late October 2004, in Bangalore, under the mentorship of Dr. Sridhar Mitta, when like minded industry leaders gathered together and debated how India can achieve leadership position in the semiconductor space similar to IT and software.

Janakiraman said: "We have come a long way since then and today ISA is recognized by everyone in the country and all such bodies outside, as the sole representation of the Indian semiconductor industry. This has been a significant achievement and made possible by all."

Today, there is a good presence of both Indian and MNC organizations, large as well as start-up companies, design, as well as manufacturing organizations, with the members of ISA now totaling 130! The ISA also works closely with central and state governments to give shape to the aspiration of our industry. It had played a key role in framing the semiconductor policy that enables larger investments in the semiconductor manufacturing ecosystem.

He added: "India has excelled in areas that are knowledge intensive. Semiconductor design is no exception, and today, we lead the world through execution of most complex and latest technology designs. The market size of the IC design and embedded software industry in India was $6 billion in 2007 and has the potential to grow into $43 billion by 2015. It currently employs around 130,000 engineering professionals."

ISA Technovation Awards
One of the primary charters of the ISA is the talent initiative. This initiative focuses not only on generation of quality talent aligned to the needs of the industry, but also to recognize innovation and research, that further nurtures talent.

The Technovation Awards were created in 2007 to recognize excellence in Academia that has made us what we are today. These awards have been created to honour semiconductor research in India and to create role models in core technology areas.

The award categories are:
1. TechnoVisionary for life time achievement in the semiconductor area
2. TechnoShield for research entity, lab or a department for excellence in a semiconductor domain of interest
3. TechnoMentor for recognizing academician/researcher for contribution in the semiconductor area
4. TechnoInventor for individual excellence in doctoral/masters researchers

This year, ISA has created two special awards for recognizing researchers from Karnataka which have been instituted by VLSI 2007 committee, under two categories:

1. Best Faculty award
2. Best PG student award

The number of nominations went up multifold in this year and an able set of panelists had a tough task of selecting the award winners.

"Given the vibrant scenario of the industry and importance of the event, we have our great leader and visionary Dr. Abdul Kalam with us today evening to recognize the award winners in person'" added Janakiraman.

"Dr. Kalam had been a role model especially for the younger generation – who are the future of this country. Dr. Kalam has been a visionary and a great inspiration for the community present here. It is a great honour for ISA to have Dr. Kalam amongst us."

The Award Winners @ Technovation 2008

Technovisionary

Juzer M. Vasi, Deputy Director, Indian Institute of Technology, IIT Bombay

TechnoMentor

Bhargab B. Bhattacharya, Professor and Officiating Deputy Director, ISI Calcutta

TechnoShield 2008 (Rolling Shield)

Indian Institute of Technology, Madras -- Semiconductor Devices Circuits & Systems Group (SDCS)

TechnoInventors

(Ph. D category)

Debdeep Mukhopadhyay, Indian Institute of Technology, Kharagpur
Thesis : Design and Analysis of Cellular Automata Based Cryptographic Algorithms

BP Harish, Indian Institute of Science, Bangalore
Thesis: Process Variability –aware Performance Modeling in 65 nm CMOS

D. Mahaveer Sathaiya, Indian Institute of Technology, Madras
Thesis: Modeling of Gate Leakage in Aigan/Gan hemts and nitride oxides

(M Tech category)

Rakesh Gnana David J, Indian Institute of Science, Bangalore
Thesis: Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

Nayan Bhogilal Patel, Indian Institute of Science, Bangalore
Thesis: Performance Enhancement of the Tunnel Field Effect Transistor for Future Low Stand-by Power Applications

Former president of India, Dr. APJ Abdul Kalam, Chief Guest at the function, advised the Indian semiconductor industry to develop tailor-made chips so that electronic equipment could become more cheaper and competitive.