SAN JOSE, USA: Cadence Design Systems Inc. recentlyintroduced the first unified TLM-driven design and verification solution and methodology enabling SoC designers to reap the benefits of transaction-level modeling (TLM).
The Cadence solution combines C-to-Silicon Compiler with new memory compiler integration and C/C++ usability, Incisive Enterprise Simulator with new TLM/RTL metric-driven verification and source level debug visualization, Calypto sequential logic equivalence checking, the first version of the TLM-driven design and verification methodology, and customer adoption services.
The solution enables SoC TLM IP to be designed, synthesized and verified, resulting in faster design creation, increased functional verification productivity, and more opportunities to reuse design and verification IP.
“We have been employing high-level synthesis and TLM verification for several years, and verification methodology has proven to be quite challenging,” said Raimund Soenning, hardware development manager, Graphics Competence Center, Fujitsu Microelectronics GmbH.
“The Cadence methodology addresses the challenges we’ve experienced applying metric-driven verification from TLM through RTL, and mixing the two. We see significant opportunities to increase the reuse of our design and verification IP by following the comprehensive Cadence methodology.”
The new TLM-driven design and verification methodology encompasses SystemC modeling guidelines for virtual platforms and high-level synthesis, and defines the process for performing multi-language OVM-based functional verification of TLM, TLM/RTL, and RTL.
The methodology will be delivered in the form of manuals, self-paced tutorials, and workshops with hands-on labs. New solution capabilities include migration from C/C++ to enable automatic conversion of legacy design sources to SystemC TLM; high-level synthesis integrated with popular memory compilers to optimize for each architecture; and side-by-side analysis and traceability of SystemC and synthesized RTL.
The new TLM-driven methodology improves productivity, design quality, and project schedule predictability. Unlike prior technology, this comprehensive new solution enables customers to reuse TLM design and verification IP as golden source.
“Cadence is uniquely positioned to combine design and verification of TLM/RTL environments to address critical barriers to adoption,” said Michael McNamara, vice president and general manager, systems software group, Cadence Design Systems. “Focusing on the complete needs of the customer, we are delivering on the full promise of system-level design productivity.”
Showing posts with label Calypto. Show all posts
Showing posts with label Calypto. Show all posts
Monday, July 20, 2009
Tuesday, June 23, 2009
Calypto delivers industry’s first automated tool for memory power optimization
SANTA CLARA, USA: Enabling a breakthrough in automated system on a chip (SoC) design, Calypto Design Systems Inc. announced the availability of its PowerPro MG (memory gating) tool.
The new tool is the industry’s first product that automatically generates power-optimized RTL by taking advantage of the low-power modes available in today’s leading on-chip memories. Employing a new “memory gating” technique, PowerPro MG eliminates costly and time-consuming manual coding. PowerPro MG will debut at this year’s Design Automation Conference (DAC) in San Francisco.
“As a supplier to leading systems companies and seven out of the top 10 SoC providers, we are constantly challenged to deliver products that enable our customers to meet ever-tightening power budgets,” said Tom Sandoval, chief executive officer of Calypto Design Systems.
“Memory can account for up to 70 percent of the power consumed in an SoC. With PowerPro MG, designers can, for the first time, apply sequential analysis techniques to automatically generate memory gating logic that significantly reduces both static and dynamic on-chip memory power.”
Currently, the design of logic used to control low-power memory modes requires hand-coding that is time-consuming and error-prone. By automatically generating logic to control low-power modes, PowerPro MG enables the lowest-power SoC possible and reduces that portion of the design cycle from weeks to hours.
Similar to its innovative PowerPro CG (clock gating) product, Calypto’s PowerPro MG fits seamlessly into today’s RTL synthesis flows. The tool reads in an RTL design written in VHDL or Verilog as well as the applicable memory models.
Using Calypto’s patented sequential analysis technology, the tool constructs new memory gating logic that works in conjunction with the low-power memory modes to produce the lowest power memory implementation possible.
PowerPro MG then generates new power-optimized RTL that looks identical to the original RTL except for the addition of the new memory gating logic. Aimed at large, complex SoC designs, PowerPro MG has been proven to reduce power consumption in a variety of end applications such as storage, networking, graphics and multimedia.
Supports leading memory IP
During the development of PowerPro MG, Calypto worked with Virage Logic, the semiconductor industry’s trusted IP partner and leading embedded memory IP provider, to maximize the opportunity for memory power savings.
“As the leader in RTL power optimization, Calypto is breaking new ground with the automation of a critical part of the SoC power optimization process,” said Brani Buric, executive vice president, marketing and sales, of Virage Logic. “Using PowerPro MG in conjunction with Virage Logic’s SiWare memory products will help enable our customers to deliver designs that are as power-efficient as possible.”
PowerPro MG works together with Calypto’s PowerPro CG product to produce the lowest power design possible. PowerPro CG reduces power by implementing sequential clock gating logic in the non-memory portions of an RTL design.
Calypto’s SLEC product is used as part of a fully automated power optimization flow to comprehensively verify that the new power optimized RTL is functionally equivalent to the original RTL. Like PowerPro CG, the new PowerPro MG has no impact on the area or performance of a design.
“To achieve the lowest power implementations in today’s complex SoCs, both static and dynamic power of logic and memory must be addressed. The flow must include multi-cycle sequential analysis for optimization and verification,” said Dr. Gary Delp, VP and technical director of the Spirit Consortium and Co-Chair of the IEEE1801, Standard for Design and Verification of Low Power Integrated Circuits Committee. “Calypto’s PowerPro family delivers an extremely effective and unique solution to SoC design teams.”
Highlighting its full suite of PowerPro and SLEC products, Calypto will demonstrate its new PowerPro MG product at this year’s Design Automation Conference (DAC) in booth #1610, being held July 26-31 in San Francisco.
Available now, Calypto’s PowerPro MG runs on PC platforms running Linux and is priced at $295K for a one year time based license.
The new tool is the industry’s first product that automatically generates power-optimized RTL by taking advantage of the low-power modes available in today’s leading on-chip memories. Employing a new “memory gating” technique, PowerPro MG eliminates costly and time-consuming manual coding. PowerPro MG will debut at this year’s Design Automation Conference (DAC) in San Francisco.
“As a supplier to leading systems companies and seven out of the top 10 SoC providers, we are constantly challenged to deliver products that enable our customers to meet ever-tightening power budgets,” said Tom Sandoval, chief executive officer of Calypto Design Systems.
“Memory can account for up to 70 percent of the power consumed in an SoC. With PowerPro MG, designers can, for the first time, apply sequential analysis techniques to automatically generate memory gating logic that significantly reduces both static and dynamic on-chip memory power.”
Currently, the design of logic used to control low-power memory modes requires hand-coding that is time-consuming and error-prone. By automatically generating logic to control low-power modes, PowerPro MG enables the lowest-power SoC possible and reduces that portion of the design cycle from weeks to hours.
Similar to its innovative PowerPro CG (clock gating) product, Calypto’s PowerPro MG fits seamlessly into today’s RTL synthesis flows. The tool reads in an RTL design written in VHDL or Verilog as well as the applicable memory models.
Using Calypto’s patented sequential analysis technology, the tool constructs new memory gating logic that works in conjunction with the low-power memory modes to produce the lowest power memory implementation possible.
PowerPro MG then generates new power-optimized RTL that looks identical to the original RTL except for the addition of the new memory gating logic. Aimed at large, complex SoC designs, PowerPro MG has been proven to reduce power consumption in a variety of end applications such as storage, networking, graphics and multimedia.
Supports leading memory IP
During the development of PowerPro MG, Calypto worked with Virage Logic, the semiconductor industry’s trusted IP partner and leading embedded memory IP provider, to maximize the opportunity for memory power savings.
“As the leader in RTL power optimization, Calypto is breaking new ground with the automation of a critical part of the SoC power optimization process,” said Brani Buric, executive vice president, marketing and sales, of Virage Logic. “Using PowerPro MG in conjunction with Virage Logic’s SiWare memory products will help enable our customers to deliver designs that are as power-efficient as possible.”
PowerPro MG works together with Calypto’s PowerPro CG product to produce the lowest power design possible. PowerPro CG reduces power by implementing sequential clock gating logic in the non-memory portions of an RTL design.
Calypto’s SLEC product is used as part of a fully automated power optimization flow to comprehensively verify that the new power optimized RTL is functionally equivalent to the original RTL. Like PowerPro CG, the new PowerPro MG has no impact on the area or performance of a design.
“To achieve the lowest power implementations in today’s complex SoCs, both static and dynamic power of logic and memory must be addressed. The flow must include multi-cycle sequential analysis for optimization and verification,” said Dr. Gary Delp, VP and technical director of the Spirit Consortium and Co-Chair of the IEEE1801, Standard for Design and Verification of Low Power Integrated Circuits Committee. “Calypto’s PowerPro family delivers an extremely effective and unique solution to SoC design teams.”
Highlighting its full suite of PowerPro and SLEC products, Calypto will demonstrate its new PowerPro MG product at this year’s Design Automation Conference (DAC) in booth #1610, being held July 26-31 in San Francisco.
Available now, Calypto’s PowerPro MG runs on PC platforms running Linux and is priced at $295K for a one year time based license.
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