Cadence expands proven NAND flash design IP offering with ONFI 3 PHY and controller

SAN JOSE, USA: Leveraging its experience in the Flash IP market, Cadence Design Systems Inc. has expanded its Flash IP offering to include support for the Open NAND Flash Interface (ONFI) 3.0 specification.

Cadence is the first company to provide a combined ONFI 3 controller and PHY IP solution, significantly streamlining SoC and system design while ensuring an optimized ONFI 3 implementation for maximum performance. Cadence Flash IP, including the broad portfolio of Denali IP acquired in 2010, has now been implemented by over 40 customers worldwide.

“System designers today see memory as a primary bandwidth bottleneck, which has given rise to many new interface standards intended to simplify design and improve overall system throughput,” said Vishal Kapoor, VP, product marketing, SoC Realization at Cadence. “As the leading supplier of memory and storage IP, Cadence applies its expertise in memory subsystem design to rapidly deliver solutions supporting the latest standards, and to implement those solutions with a highly efficient architecture designed for maximum performance.”

The ONFI 3 specification simplifies the design of high-performance computing platforms, such as solid state drives and enterprise storage solutions; and consumer devices, such as tablets and smartphones that integrate NAND Flash memory. The new specification defines speeds of up to 400 mega-transfers per second. In addition to the new ONFI 3 specification, the Cadence Flash and controller IP also support the Toggle 2.0 specification.

"NAND flash is very dramatically growing in the computing segment and is no longer just for storing songs, photos, and videos," said Jim Handy, director, at Objective Analysis. "The result is that the bulk of future NAND growth will consist of chips sporting high-speed interfaces. Cadence support of ONFI 3 and other high-speed interfaces is coming at the right time for designers of SSDs and other systems."

The Cadence controller and PHY IP implement advanced capabilities of the standard including chip-enable interleaving, which results in significantly improved system performance when dealing with multiple flash devices, as has become common in high-end mobile devices and SSDs. As a result, the IP can deliver up to 95 percent of a NAND device’s theoretical maximum throughput.

Cadence implements sophisticated, highly configurable error correction techniques to further enhance performance and deliver enterprise class reliability. Delivering advanced configurability, low-power capabilities and support for system boot from NAND, the Cadence solution is scalable from mobile applications to the data center.

The IP is backward-compatible with existing ONFI and Toggle standards. The existing Cadence IP offering supports the ONFI 1, ONFI 2, Toggle 1 and Toggle 2 specifications, and also provides asynchronous device support.

The Cadence ONFI 3 memory controller and PHY IP are available now. Cadence also offers supporting verification IP (VIP) and memory models to ensure successful implementation.